Merge branch 'net' of git://www.denx.de/git/u-boot-microblaze
[platform/kernel/u-boot.git] / board / freescale / c29xpcie / tlb.c
index ddd1ef8..c5abed0 100644 (file)
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,14 +44,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_256K, 1),
 #endif
+#endif
 
        SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 4, BOOKE_PAGESZ_4K, 1),
+                       0, 4, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 5, BOOKE_PAGESZ_16K, 1),
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 5, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
                        CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 7, BOOKE_PAGESZ_256K, 1),
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+               (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
                        CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);