powerpc/b4860: fix for Serdes connectivity to SFP's

[platform/kernel/u-boot.git] / board / freescale / b4860qds / b4860qds.c

diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 88bdc1f..a39c17a 100644 (file)
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -50,7 +50,7 @@ int checkboard(void)
 {
        char buf[64];
        u8 sw;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;
        static const char *const freq[] = {"100", "125", "156.25", "161.13",
@@ -166,11 +166,13 @@ int configure_vsc3316_3308(void)
                ret = select_i2c_ch_pca(I2C_CH_VSC3316);
                if (!ret) {
                        ret = vsc3316_config(VSC3316_TX_ADDRESS,
-                                       vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+                                       vsc16_tx_4sfp_sgmii_12_56,
+                                       num_vsc16_con);
                        if (ret)
                                return ret;
                        ret = vsc3316_config(VSC3316_RX_ADDRESS,
-                                       vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+                                       vsc16_rx_4sfp_sgmii_12_56,
+                                       num_vsc16_con);
                        if (ret)
                                return ret;
                } else {
@@ -456,3 +458,50 @@ void ft_board_setup(void *blob, bd_t *bd)
        fdt_fixup_board_enet(blob);
 #endif
 }
+
+/*
+ * Dump board switch settings.
+ * The bits that cannot be read/sampled via some FPGA or some
+ * registers, they will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+       int i;
+       u8 sw[5];
+
+       /*
+        * Any bit with 1 means that bit cannot be reverse engineered.
+        * It will be displayed as _ in binary format.
+        */
+       static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
+       char buf[10];
+       u8 brdcfg[16], dutcfg[16];
+
+       for (i = 0; i < 16; i++) {
+               brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+               dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+       }
+
+       sw[0] = ((brdcfg[0] & 0x0f) << 4)       | \
+               (brdcfg[9] & 0x08);
+       sw[1] = ((dutcfg[1] & 0x01) << 7)       | \
+               ((dutcfg[2] & 0x07) << 4)       | \
+               ((dutcfg[6] & 0x10) >> 1)       | \
+               ((dutcfg[6] & 0x80) >> 5)       | \
+               ((dutcfg[1] & 0x40) >> 5)       | \
+               (dutcfg[6] & 0x01);
+       sw[2] = dutcfg[0];
+       sw[3] = 0;
+       sw[4] = ((brdcfg[1] & 0x30) << 2)       | \
+               ((brdcfg[1] & 0xc0) >> 2)       | \
+               (brdcfg[1] & 0x0f);
+
+       puts("DIP switch settings:\n");
+       for (i = 0; i < 5; i++) {
+               printf("SW%d         = 0b%s (0x%02x)\n",
+                       i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+       }
+}