ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / esd / voh405 / voh405.c

diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index ec65ffd..7477f56 100644 (file)
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -99,7 +99,7 @@ int board_early_init_f (void)
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
         */
-       mtebc (epcr, 0xa8400000); /* ebc always driven */
+       mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 
        return 0;
 }
@@ -297,18 +297,18 @@ int checkboard (void)
 }
 
 #ifdef CONFIG_IDE_RESET
+#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 void ide_set_reset(int on)
 {
-       volatile unsigned short *fpga_mode =
-               (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-
        /*
         * Assert or deassert CompactFlash Reset Pin
         */
        if (on) {               /* assert RESET */
-               *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
+               out_be16((void *)FPGA_MODE,
+                        in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
        } else {                /* release RESET */
-               *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
+               out_be16((void *)FPGA_MODE,
+                        in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
        }
 }
 #endif /* CONFIG_IDE_RESET */
@@ -392,6 +392,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(eepwren,    2,      0,      do_eep_wren,
-          "eepwren - Enable / disable / query EEPROM write access\n",
-          NULL);
+       "Enable / disable / query EEPROM write access",
+       ""
+);
 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */