* (C) Copyright 2007
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
#include <common.h>
{
debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
__LINE__);
- fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
+ fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
}
int fpga_pre_config_fn(int cookie)
{
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(true);
+ fpga_reset(TRUE);
/* release init# */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
/* enable PLD0..7 pins */
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
- fpga_reset(true);
+ fpga_reset(TRUE);
udelay (100);
- fpga_reset(false);
+ fpga_reset(FALSE);
udelay (100);
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
__FUNCTION__, __LINE__);
/* make sure program pin is inactive */
- ngcc_fpga_pgm_fn(false, false, 0);
+ ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
}
/*
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- ngcc_fpga_reset(true);
+ ngcc_fpga_reset(TRUE);
FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
- ngcc_fpga_reset(true);
+ ngcc_fpga_reset(TRUE);
return 0;
}
debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
udelay (100);
- ngcc_fpga_reset(false);
+ ngcc_fpga_reset(FALSE);
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);