/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/processor.h>
#include <command.h>
-#include <cmd_boot.h>
#include <malloc.h>
#include <pci.h>
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/io.h>
#include "pci405.h"
+DECLARE_GLOBAL_DATA_PTR;
-/* ------------------------------------------------------------------------- */
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
#if 0
#define FPGA_DEBUG
#endif
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] =
{
*/
#include "../common/fpga.c"
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
-int board_pre_init (void)
+int board_revision(void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Get version of PCI405 board from GPIO's
+ */
+
+ /*
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ switch (value) {
+ case 0x00100200:
+ /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+ return 1;
+ case 0x00000200:
+ /* CS2==0 && IRQ5==1 -> version 1.2 */
+ return 2;
+ case 0x00000000:
+ /* CS2==0 && IRQ5==0 -> version 1.3 */
+ return 3;
+#if 0 /* not yet manufactured ! */
+ case 0x00100000:
+ /* CS2==1 && IRQ5==0 -> version 1.4 */
+ return 4;
+#endif
+ default:
+ /* should not be reached! */
+ return 0;
+ }
+}
+
+
+unsigned long fpga_done_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_DONE_STATE_V11;
+ } else {
+ return FPGA_DONE_STATE_V12;
+ }
+}
+
+
+unsigned long fpga_init_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_INIT_STATE_V11;
+ } else {
+ return FPGA_INIT_STATE_V12;
+ }
+}
+
+
+int board_early_init_f (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /*
+ * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+ */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
/*
* Setup GPIO pins (IRQ4/GPIO21 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00008000);
-
- return 0;
-}
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
+ /*
+ * Setup GPIO pins (CS6+CS7 as GPIO)
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-/* ------------------------------------------------------------------------- */
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
+ return 0;
}
-
int misc_init_r (void)
{
unsigned char *dst;
* FPGA can be gzip compressed (malloc) and booted this late.
*/
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
* Rewrite pci config regs (only after soft-reset with magic set)
*/
ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
puts("Restoring PCI Configurations Regs!\n");
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
for (i=0; i<0x40; i+=4) {
}
}
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-
+
*magic = 0; /* clear pci reconfig magic again */
}
+ /*
+ * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+ */
+#define PCI0_BRDGOPT1 0x4a
+ pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+
+#define PLB0_ACR 0x87
+ /*
+ * Enable fairness and high bus utilization
+ */
+ mtdcr(PLB0_ACR, 0x98000000);
+
free(dst);
return (0);
}
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
} else {
puts (str);
}
- putc ('\n');
- return 0;
-}
+ gd->board_type = board_revision();
+ printf(" (Rev 1.%ld", gd->board_type);
-/* ------------------------------------------------------------------------- */
-
-long int initdram (int board_type)
-{
- unsigned long val;
+ if (gd->board_type >= 2) {
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
+ /*
+ * Setup GPIO pins (Trace/GPIO1 to GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
+ if (value) {
+ puts(", 33 MHz PCI");
+ } else {
+ puts(", 66 MHz PCI");
+ }
+ }
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
+ puts(")\n");
-#if 0 /* test-only: all PCI405 version must report 16mb */
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-#else
- return (16*1024*1024);
-#endif
+ return 0;
}
/* ------------------------------------------------------------------------- */
+#define UART1_MCR 0xef600404
+int wpeeprom(int wp)
+{
+ int wp_state = wp;
-int testdram (void)
+ if (wp == 1) {
+ out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
+ } else if (wp == 0) {
+ out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
+ } else {
+ if (in_8((void *)UART1_MCR) & 0x02) {
+ wp_state = 0;
+ } else {
+ wp_state = 1;
+ }
+ }
+ return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
+ int wp = -1;
+ if (argc >= 2) {
+ if (argv[1][0] == '1') {
+ wp = 1;
+ } else if (argv[1][0] == '0') {
+ wp = 0;
+ }
+ }
- return (0);
+ wp = wpeeprom(wp);
+ printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+ return 0;
}
-/* ------------------------------------------------------------------------- */
+U_BOOT_CMD(
+ wpeeprom, 2, 1, do_wpeeprom,
+ "Check/Enable/Disable I2C EEPROM write protection",
+ "wpeeprom\n"
+ " - check I2C EEPROM write protection state\n"
+ "wpeeprom 1\n"
+ " - enable I2C EEPROM write protection\n"
+ "wpeeprom 0\n"
+ " - disable I2C EEPROM write protection"
+);
projects / platform / kernel / u-boot.git / blobdiff