ppc4xx: Consolidate pci_target_init() function

[kernel/u-boot.git] / board / esd / du440 / du440.c

diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 8f9f950..866dcaf 100644 (file)
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -414,73 +414,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*
-        * Set up Direct MMIO registers
-        */
-       /*
-        * PowerPC440EPX PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        * PLB address 0xA0000000-0xDFFFFFFF
-        *     ==> PCI address 0xA0000000-0xDFFFFFFF
-        * Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             PCI_VENDOR_ID_ESDGMBH);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
-
-       pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {