tizen 2.3.1 release

[platform/kernel/u-boot.git] / board / esd / dasa_sim / cmd_dasa_sim.c

diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index 9191624..4946538 100644 (file)
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -2,7 +2,24 @@
  * (C) Copyright 2001
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  */
 
 #include <common.h>
@@ -13,6 +30,10 @@
 #define OK 0
 #define ERROR (-1)
 
+#define TRUE 1
+#define FALSE 0
+
+
 extern u_long pci9054_iobase;
 
 
@@ -76,7 +97,7 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value)
                }
        }
 
-       return true;
+       return TRUE;
 }
 
 
@@ -111,6 +132,8 @@ static void showPci9054 (void)
 
 static void updatePci9054 (void)
 {
+       int val;
+
        /*
         * Set EEPROM write-protect register to 0
         */
@@ -118,44 +141,44 @@ static void updatePci9054 (void)
                  in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
 
        /* Long Serial EEPROM Load Registers... */
-       PciEepromWriteLongVPD (0x00, 0x905410b5);
-       PciEepromWriteLongVPD (0x04, 0x09800001);       /* other input controller */
-       PciEepromWriteLongVPD (0x08, 0x28140100);
+       val = PciEepromWriteLongVPD (0x00, 0x905410b5);
+       val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
+       val = PciEepromWriteLongVPD (0x08, 0x28140100);
 
-       PciEepromWriteLongVPD (0x0c, 0x00000000);       /* MBOX0... */
-       PciEepromWriteLongVPD (0x10, 0x00000000);
+       val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
+       val = PciEepromWriteLongVPD (0x10, 0x00000000);
 
        /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
-       PciEepromWriteLongVPD (0x14, 0xfffc0000);       /* LAS0RR... */
-       PciEepromWriteLongVPD (0x18, 0x00000001);       /* LAS0BA */
+       val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
+       val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
 
-       PciEepromWriteLongVPD (0x1c, 0x00200000);       /* MARBR... */
-       PciEepromWriteLongVPD (0x20, 0x00300500);       /* LMISC/BIGEND */
+       val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
+       val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
 
-       PciEepromWriteLongVPD (0x24, 0x00000000);       /* EROMRR... */
-       PciEepromWriteLongVPD (0x28, 0x00000000);       /* EROMBA */
+       val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
+       val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
 
-       PciEepromWriteLongVPD (0x2c, 0x43030000);       /* LBRD0... */
+       val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
 
-       PciEepromWriteLongVPD (0x30, 0x00000000);       /* DMRR... */
-       PciEepromWriteLongVPD (0x34, 0x00000000);
-       PciEepromWriteLongVPD (0x38, 0x00000000);
+       val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
+       val = PciEepromWriteLongVPD (0x34, 0x00000000);
+       val = PciEepromWriteLongVPD (0x38, 0x00000000);
 
-       PciEepromWriteLongVPD (0x3c, 0x00000000);       /* DMPBAM... */
-       PciEepromWriteLongVPD (0x40, 0x00000000);
+       val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
+       val = PciEepromWriteLongVPD (0x40, 0x00000000);
 
        /* Extra Long Serial EEPROM Load Registers... */
-       PciEepromWriteLongVPD (0x44, 0x010212fe);       /* PCISID... */
+       val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
 
        /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
        /* Offset to LAS1: Group 1: 0x00040000                 */
        /*                 Group 2: 0x00080000                 */
        /*                 Group 3: 0x000c0000                 */
-       PciEepromWriteLongVPD (0x48, 0xffe00000);       /* LAS1RR */
-       PciEepromWriteLongVPD (0x4c, 0x00040001);       /* LAS1BA */
-       PciEepromWriteLongVPD (0x50, 0x00000208);       /* LBRD1 */ /* so wars bisher */
+       val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
+       val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
+       val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
 
-       PciEepromWriteLongVPD (0x54, 0x00004c06);       /* HotSwap... */
+       val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
 
        printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
 }
@@ -163,6 +186,8 @@ static void updatePci9054 (void)
 
 static void clearPci9054 (void)
 {
+       int val;
+
        /*
         * Set EEPROM write-protect register to 0
         */
@@ -170,8 +195,8 @@ static void clearPci9054 (void)
                  in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
 
        /* Long Serial EEPROM Load Registers... */
-       PciEepromWriteLongVPD (0x00, 0xffffffff);
-       PciEepromWriteLongVPD (0x04, 0xffffffff);       /* other input controller */
+       val = PciEepromWriteLongVPD (0x00, 0xffffffff);
+       val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
 
        printf ("Finished clearing PLX PCI9054 EEPROM!\n");
 }