/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
-#include <cmd_boot.h>
#include <malloc.h>
+#include <net.h>
+#include <pci.h>
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
const unsigned char fpgadata[] =
{
#ifdef CONFIG_CPCI405_VER2
-# include "fpgadata_cpci4052.c"
+# ifdef CONFIG_CPCI405AB
+# include "fpgadata_cpci405ab.c"
+# else
+# include "fpgadata_cpci4052.c"
+# endif
#else
# include "fpgadata_cpci405.c"
#endif
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
+#include "../common/auto_update.h"
+
+#ifdef CONFIG_CPCI405AB
+au_image_t au_image[] = {
+ {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+ {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+ {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#ifdef CONFIG_CPCI405_VER2
+au_image_t au_image[] = {
+ {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+ {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+ {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+ {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+ {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+ {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */
-int version2(void);
-int gunzip(void *, int, unsigned char *, int *);
+int cpci405_version(void);
+int gunzip(void *, int, unsigned char *, unsigned long *);
+void lxt971_no_sleep(void);
-
-int board_pre_init (void)
+int board_early_init_f (void)
{
#ifndef CONFIG_CPCI405_VER2
int index, len, i;
#endif
#ifdef FPGA_DEBUG
- DECLARE_GLOBAL_DATA_PTR;
-
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
- out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
- out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
- out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
+ out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
*/
#ifndef CONFIG_CPCI405_VER2
- if (!version2()) {
+ if (cpci405_version() == 1) {
status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
if (status != 0) {
/* booting FPGA failed */
#ifndef FPGA_DEBUG
- DECLARE_GLOBAL_DATA_PTR;
-
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+#ifdef CONFIG_CPCI405_6U
+ if (cpci405_version() == 3) {
+ mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
+ } else {
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ }
+#else
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+#endif
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
-
/* ------------------------------------------------------------------------- */
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
else
- return -1; /* yes, board is cterm-m2 */
+ return -1; /* yes, board is cterm-m2 */
#endif
}
-
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- return -1; /* yes, board is cpci405 host */
+ return -1; /* yes, board is cpci405 host */
else
- return 0; /* no, board is cpci405 adapter */
+ return 0; /* no, board is cpci405 adapter */
}
-
-int version2(void)
+int cpci405_version(void)
{
unsigned long cntrl0Reg;
unsigned long value;
/*
- * Setup GPIO pins (CS2/GPIO11 as GPIO)
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x02000000);
-
- udelay(1000); /* wait some time before reading input */
- value = in32(IBM405GP_GPIO0_IR) & 0x00100000; /* test GPIO11 */
+ mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
- * Setup GPIO pins (CS2/GPIO11 as CS again)
+ * Restore GPIO settings
*/
mtdcr(cntrl0, cntrl0Reg);
- if (value)
- return 0; /* no, board is version 1.x */
- else
- return -1; /* yes, board is version 2.x */
-}
-
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
+ switch (value) {
+ case 0x00180000:
+ /* CS2==1 && CS3==1 -> version 1 */
+ return 1;
+ case 0x00080000:
+ /* CS2==0 && CS3==1 -> version 2 */
+ return 2;
+ case 0x00100000:
+ /* CS2==1 && CS3==0 -> version 3 or 6U board */
+ return 3;
+ case 0x00000000:
+ /* CS2==0 && CS3==0 -> version 4 */
+ return 4;
+ default:
+ /* should not be reached! */
+ return 2;
+ }
}
-
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
+ unsigned long cntrl0Reg;
- bd_t *bd = gd->bd;
- char * tmp; /* Temporary char pointer */
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
#ifdef CONFIG_CPCI405_VER2
+ {
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
- unsigned long cntrl0Reg;
/*
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
-
- if (version2()) {
+ if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
putc ('\n');
free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+#ifdef CONFIG_CPCI405_6U
+ if (cpci405_version() == 3) {
+ volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+ volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
+
+ /*
+ * Enable outputs in fpga on version 3 board
+ */
+ *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
+
+ /*
+ * Set outputs to 0
+ */
+ *leds = 0x00;
+
+ /*
+ * Reset external DUART
+ */
+ *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
+ udelay(100);
+ *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
+ }
+#endif
}
else {
- printf("\n*** U-Boot Version does not match Board Version!\n");
- printf("*** CPCI-405 Version 2.x detected!\n");
- printf("*** Please use correct U-Boot version (CPCI4052)!\n\n");
+ puts("\n*** U-Boot Version does not match Board Version!\n");
+ puts("*** CPCI-405 Version 1.x detected!\n");
+ puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+ }
}
#else /* CONFIG_CPCI405_VER2 */
+#if 0 /* test-only: code-plug now not relavant for ip-address any more */
/*
* Generate last byte of ip-addr from code-plug @ 0xf0000400
*/
setenv("ipaddr", str);
}
}
+#endif
- if (version2()) {
- printf("\n*** U-Boot Version does not match Board Version!\n");
- printf("*** CPCI-405 Board Version 1.x detected!\n");
- printf("*** Please use correct U-Boot version (CPCI405)!\n\n");
+ if (cpci405_version() >= 2) {
+ puts("\n*** U-Boot Version does not match Board Version!\n");
+ puts("*** CPCI-405 Board Version 2.x detected!\n");
+ puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
}
#endif /* CONFIG_CPCI405_VER2 */
/*
- * Write ethernet addr in NVRAM for VxWorks
+ * Select cts (and not dsr) on uart1
*/
- tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
- memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
return (0);
}
-
/*
* Check Board Identity:
*/
int index;
int len;
#endif
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
+ unsigned short ver;
puts ("Board: ");
puts(str);
}
- if (version2())
- puts (" (Ver 2.x, ");
- else
- puts (" (Ver 1.x, ");
+ ver = cpci405_version();
+ printf(" (Ver %d.x, ", ver);
-#if 0
- if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS)
- & CFG_FPGA_STATUS_FLASH)
- puts ("FLASH Bank A, ");
- else
- puts ("FLASH Bank B, ");
+#if 0 /* test-only */
+ if (ver >= 2) {
+ volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
+
+ if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
+ puts ("FLASH Bank B, ");
+ } else {
+ puts ("FLASH Bank A, ");
+ }
+ }
#endif
if (ctermm2()) {
- printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
+ char str[4];
+
+ /*
+ * Read board-id and save in env-variable
+ */
+ sprintf(str, "%d", *(unsigned char *)0xf0000400);
+ setenv("boardid", str);
+ printf("CTERM-M2 - Id=%s)", str);
} else {
if (cpci405_host()) {
puts ("PCI Host Version)");
}
#ifndef CONFIG_CPCI405_VER2
- puts ("\nFPGA: ");
+ puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
#endif
putc ('\n');
-
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-long int initdram (int board_type)
+void reset_phy(void)
{
- unsigned long val;
+#ifdef CONFIG_LXT971_NO_SLEEP
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
}
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */
-/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = 0xff;
+
+ /*
+ * Write pci interrupt line register (cpci405 specific)
+ */
+ switch (PCI_DEV(dev) & 0x03) {
+ case 0:
+ int_line = 27 + 2;
+ break;
+ case 1:
+ int_line = 27 + 3;
+ break;
+ case 2:
+ int_line = 27 + 0;
+ break;
+ case 3:
+ int_line = 27 + 1;
+ break;
+ }
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = cpci405_pci_fixup_irq;
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+#ifdef CONFIG_CPCI405AB
+
+#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+ |= CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+ &= ~CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+ & CFG_FPGA_MODE_1WIRE)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
+{
+ int result;
+
+ ONE_WIRE_CLEAR;
+ udelay(480);
+ ONE_WIRE_SET;
+ udelay(70);
+
+ result = ONE_WIRE_GET;
+
+ udelay(410);
+ return result;
+}
+
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
+{
+ if (bit) {
+ /*
+ * write '1' bit
+ */
+ ONE_WIRE_CLEAR;
+ udelay(6);
+ ONE_WIRE_SET;
+ udelay(64);
+ } else {
+ /*
+ * write '0' bit
+ */
+ ONE_WIRE_CLEAR;
+ udelay(60);
+ ONE_WIRE_SET;
+ udelay(10);
+ }
+}
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+ int result;
+
+ ONE_WIRE_CLEAR;
+ udelay(6);
+ ONE_WIRE_SET;
+ udelay(9);
+
+ result = ONE_WIRE_GET;
+
+ udelay(55);
+ return result;
+}
+
+void OWWriteByte(int data)
+{
+ int loop;
+
+ for (loop=0; loop<8; loop++) {
+ OWWriteBit(data & 0x01);
+ data >>= 1;
+ }
+}
+
+int OWReadByte(void)
+{
+ int loop, result = 0;
+
+ for (loop=0; loop<8; loop++) {
+ result >>= 1;
+ if (OWReadBit()) {
+ result |= 0x80;
+ }
+ }
+
+ return result;
+}
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ volatile unsigned short val;
+ int result;
+ int i;
+ unsigned char ow_id[6];
+ char str[32];
+ unsigned char ow_crc;
+
+ /*
+ * Clear 1-wire bit (open drain with pull-up)
+ */
+ val = *(volatile unsigned short *)0xf0400000;
+ val &= ~0x1000; /* clear 1-wire bit */
+ *(volatile unsigned short *)0xf0400000 = val;
+
+ result = OWTouchReset();
+ if (result != 0) {
+ puts("No 1-wire device detected!\n");
+ }
+
+ OWWriteByte(0x33); /* send read rom command */
+ OWReadByte(); /* skip family code ( == 0x01) */
+ for (i=0; i<6; i++) {
+ ow_id[i] = OWReadByte();
+ }
+ ow_crc = OWReadByte(); /* read crc */
+
+ sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+ printf("Setting environment variable 'ow_id' to %s\n", str);
+ setenv("ow_id", str);
+
+ return 0;
+}
+U_BOOT_CMD(
+ onewire, 1, 1, do_onewire,
+ "onewire - Read 1-write ID\n",
+ NULL
+ );
+
+#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ bd_t *bd = gd->bd;
+ char *buf;
+ ulong crc;
+ char str[32];
+ char *ptr;
+ IPaddr_t ipaddr;
+
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+ puts("\nError reading backplane EEPROM!\n");
+ } else {
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+ if (crc != *(ulong *)buf) {
+ printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+ return -1;
+ }
+
+ /*
+ * Find bp_ip
+ */
+ ptr = strstr(buf+4, "bp_ip=");
+ if (ptr == NULL) {
+ printf("ERROR: bp_ip not found!\n");
+ return -1;
+ }
+ ptr += 6;
+ ipaddr = string_to_ip(ptr);
+
+ /*
+ * Update whole ip-addr
+ */
+ bd->bi_ip_addr = ipaddr;
+ sprintf(str, "%ld.%ld.%ld.%ld",
+ (bd->bi_ip_addr & 0xff000000) >> 24,
+ (bd->bi_ip_addr & 0x00ff0000) >> 16,
+ (bd->bi_ip_addr & 0x0000ff00) >> 8,
+ (bd->bi_ip_addr & 0x000000ff));
+ setenv("ipaddr", str);
+ printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+ }
+
+ free(buf);
+
+ return 0;
+}
+U_BOOT_CMD(
+ getbpip, 1, 1, do_get_bpip,
+ "getbpip - Update IP-Address with Backplane IP-Address\n",
+ NULL
+ );
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char *buf;
+ char str[32];
+ ulong crc;
+
+ if (argc < 2) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ printf("Setting bp_ip to %s\n", argv[1]);
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ memset(buf, 0, CONFIG_ENV_SIZE_2);
+ sprintf(str, "bp_ip=%s", argv[1]);
+ strcpy(buf+4, str);
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+ *(ulong *)buf = crc;
+
+ if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+ puts("\nError writing backplane EEPROM!\n");
+ }
+
+ free(buf);
+
+ return 0;
+}
+U_BOOT_CMD(
+ setbpip, 2, 1, do_set_bpip,
+ "setbpip - Write Backplane IP-Address\n",
+ NULL
+ );
+
+#endif /* CONFIG_CPCI405AB */
projects / platform / kernel / u-boot.git / blobdiff