ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / esd / cpci405 / cpci405.c

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index ccbe245..4c9ed2f 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -214,7 +214,7 @@ int ctermm2(void)
 
 int cpci405_host(void)
 {
-       if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+       if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
                return -1;              /* yes, board is cpci405 host */
        else
                return 0;               /* no, board is cpci405 adapter */
@@ -222,14 +222,14 @@ int cpci405_host(void)
 
 int cpci405_version(void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
        unsigned long value;
 
        /*
         * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
        out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
        udelay(1000); /* wait some time before reading input */
@@ -238,7 +238,7 @@ int cpci405_version(void)
        /*
         * Restore GPIO settings
         */
-       mtdcr(cntrl0, cntrl0Reg);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
        switch (value) {
        case 0x00180000:
@@ -261,7 +261,7 @@ int cpci405_version(void)
 
 int misc_init_r (void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
 
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -283,8 +283,8 @@ int misc_init_r (void)
                /*
                 * Setup GPIO pins (CS6+CS7 as GPIO)
                 */
-               cntrl0Reg = mfdcr(cntrl0);
-               mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+               CPC0_CR0Reg = mfdcr(CPC0_CR0);
+               mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 
                dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
                if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
@@ -330,7 +330,7 @@ int misc_init_r (void)
                }
 
                /* restore gpio/cs settings */
-               mtdcr(cntrl0, cntrl0Reg);
+               mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
                puts("FPGA:  ");
 
@@ -400,8 +400,8 @@ int misc_init_r (void)
        /*
         * Select cts (and not dsr) on uart1
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
 
        return 0;
 }
@@ -690,8 +690,8 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
        onewire,        1,      1,      do_onewire,
        "Read 1-write ID",
-       NULL
-       );
+       ""
+);
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
@@ -751,8 +751,8 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
        getbpip,        1,      1,      do_get_bpip,
        "Update IP-Address with Backplane IP-Address",
-       NULL
-       );
+       ""
+);
 
 /*
  * Set and print backplane ip...
@@ -787,7 +787,7 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
        setbpip,        2,      1,      do_set_bpip,
        "Write Backplane IP-Address",
-       NULL
-       );
+       ""
+);
 
 #endif /* CONFIG_CPCI405AB */