ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / esd / cpci2dp / cpci2dp.c

diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index dcab906..00c7024 100644 (file)
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -30,18 +31,20 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f (void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
 
        /*
         * Setup GPIO pins
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg |
+             ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
+               CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
 
        /* set output pins to high */
-       out32(GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
+       out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
        /* setup for output (LED=off) */
-       out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
+       out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
 
        /*
         * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -69,7 +72,7 @@ int board_early_init_f (void)
 
 int misc_init_r (void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
 
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -78,8 +81,8 @@ int misc_init_r (void)
        /*
         * Select cts (and not dsr) on uart1
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
 
        return (0);
 }
@@ -124,17 +127,20 @@ int eeprom_write_enable (unsigned dev_addr, int state) {
                switch (state) {
                case 1:
                        /* Enable write access, clear bit GPIO_SINT2. */
-                       out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+                       out_be32((void *)GPIO0_OR,
+                                in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
                        state = 0;
                        break;
                case 0:
                        /* Disable write access, set bit GPIO_SINT2. */
-                       out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+                       out_be32((void *)GPIO0_OR,
+                                in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
                        state = 0;
                        break;
                default:
                        /* Read current status back. */
-                       state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+                       state = (0 == (in_be32((void *)GPIO0_OR) &
+                                      CONFIG_SYS_EEPROM_WP));
                        break;
                }
        }
@@ -176,7 +182,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
        eepwren,        2,      0,      do_eep_wren,
-       "eepwren - Enable / disable / query EEPROM write access\n",
-       NULL
-       );
+       "Enable / disable / query EEPROM write access",
+       ""
+);
 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */