#include <command.h>
#include <malloc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ------------------------------------------------------------------------- */
/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
int board_early_init_f (void)
{
- out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
+ out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
+ out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
#if 1 /* test-only */
- mtebc (epcr, 0xa8400000); /* ebc always driven */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
#else
- mtebc (epcr, 0x28400000); /* ebc in high-z */
+ mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
#endif
return 0;
}
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart = 0 - flash_info[0].size;
- gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
+ gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
#if 0
volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned char *duart0_mcr =
(unsigned char *)((ulong)DUART0_BA + 4);
volatile unsigned char *duart1_mcr =
int status;
int index;
int i;
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
/*
* Enable power on PS/2 interface
*/
- *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
/*
* Enable interrupts in exar duart mcr[3]
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0 /* test-only */
- for (;;) {
- NAND_DISABLE_CE(1);
- udelay(100);
- NAND_ENABLE_CE(1);
- udelay(100);
- }
-#endif
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
int testdram (void)
{
/* TODO: XXX XXX XXX */
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern ulong
-nand_probe(ulong physadr);
-
-void
-nand_init(void)
-{
- ulong totlen = 0;
-
-/*
- The HI model is equipped with a large block NAND chip not supported yet
- by U-Boot
- (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-*/
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
- debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
- totlen += nand_probe (CFG_NAND0_BASE);
-#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
-
- debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
- totlen += nand_probe (CFG_NAND1_BASE);
-
- printf ("%4lu MB\n", totlen >>20);
-}
-#endif
-
#ifdef CONFIG_CFB_CONSOLE
# ifdef CONFIG_CONSOLE_EXTRA_INFO
# include <video_fb.h>
case 1:
switch (pvr) {
case PVR_405EP_RB:
- sprintf (info, " IBM PowerPC 405EP Rev. B");
+ sprintf (info, " AMCC PowerPC 405EP Rev. B");
break;
default:
- sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+ sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
break;
}
return;