/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * (C) Copyright 2003
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
*
* See file CREDITS for list of people who contributed to this
* project.
/* ------------------------------------------------------------------------- */
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
-
+int gunzip(void *, int, unsigned char *, unsigned long *);
-int board_pre_init (void)
+int board_early_init_f (void)
{
out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
+ out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ * IRQ 25 (EXT IRQ 0)
+ * IRQ 26 (EXT IRQ 1)
+ * IRQ 27 (EXT IRQ 2)
+ * IRQ 28 (EXT IRQ 3)
+ * IRQ 29 (EXT IRQ 4)
+ * IRQ 30 (EXT IRQ 5)
+ * IRQ 31 (EXT IRQ 6)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
#else
mtebc (epcr, 0x28400000); /* ebc in high-z */
#endif
-
return 0;
}
-
/* ------------------------------------------------------------------------- */
int misc_init_f (void)
return 0; /* dummy implementation */
}
+extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
-#if 0 /* test-only */
DECLARE_GLOBAL_DATA_PTR;
+
+ /* adjust flash start and size as well as the offset */
+ gd->bd->bi_flashstart = 0 - flash_info[0].size;
+ gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
#if 0
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
unsigned long cntrl0Reg;
dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
-
#endif
#if 0
*duart0_mcr = 0x08;
*duart1_mcr = 0x08;
#endif
-#endif
-
return (0);
}
-
/*
* Check Board Identity:
*/
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void
+extern ulong
nand_probe(ulong physadr);
void
nand_init(void)
{
- printf("Probing at 0x%.8x\n", CFG_NAND0_BASE);
- nand_probe(CFG_NAND0_BASE);
- printf("Probing at 0x%.8x\n", CFG_NAND1_BASE);
- nand_probe(CFG_NAND1_BASE);
+ ulong totlen = 0;
+
+/*
+ The HI model is equipped with a large block NAND chip not supported yet
+ by U-Boot
+ (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+*/
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+ debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+ totlen += nand_probe (CFG_NAND0_BASE);
+#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
+
+ debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
+ totlen += nand_probe (CFG_NAND1_BASE);
+
+ printf ("%3lu MB\n", totlen >>20);
}
#endif
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+ uint pvr = get_pvr ();
+
+ /* init video info strings for graphic console */
+ switch (line_number) {
+ case 1:
+ switch (pvr) {
+ case PVR_405EP_RB:
+ sprintf (info, " IBM PowerPC 405EP Rev. B");
+ break;
+ default:
+ sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+ break;
+ }
+ return;
+ case 2:
+ sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+ return;
+ case 3:
+ sprintf (info, " %s", smi.modeIdent);
+ return;
+ }
+
+ /* no more info lines */
+ *info = 0;
+ return;
+}
+# endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_CFB_CONSOLE */
projects / platform / kernel / u-boot.git / blobdiff