#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
+#ifndef CONFIG_SPL_BUILD
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+#endif
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
return 0;
/* set level of MIPI if specified */
- lv_mipi = getenv("lv_mipi");
+ lv_mipi = env_get("lv_mipi");
if (lv_mipi)
return 0;
{
int i;
int ret;
- char const *panel = getenv("panel");
+ char const *panel = env_get("panel");
if (!panel) {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
struct display_info_t const *dev = displays + i;
return 1;
}
-static bool is_mx6q(void)
-{
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
- return true;
- else
- return false;
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- if (is_mx6q())
+ if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
setup_sata();
#endif
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_mx6q())
- setenv("board_rev", "MX6Q");
+ if (is_mx6dq())
+ env_set("board_rev", "MX6Q");
else
- setenv("board_rev", "MX6DL");
+ env_set("board_rev", "MX6DL");
#endif
return 0;
.bi_on = 1,
.sde_to_rst = 0x0d,
.rst_to_cke = 0x20,
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 7, /* 8 refresh commands per refresh cycle */
};
if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
return;
}
- if (is_mx6q()) {
+ if (is_mx6dq()) {
mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {