arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

[platform/kernel/u-boot.git] / board / compulab / cm_t35 / cm_t35.c

diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b0b80e5..d0b0930 100644 (file)
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -9,22 +9,7 @@
  *     Richard Woodruff <r-woodruff2@ti.com>
  *     Syed Mohammed Khasim <x0khasim@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -48,7 +33,7 @@
 #include <asm/ehci-omap.h>
 #include <asm/gpio.h>
 
-#include "eeprom.h"
+#include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -68,16 +53,6 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
        0
 };
 
-static u32 gpmc_nand_config[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
-       0,
-};
-
 #ifdef CONFIG_LCD
 #ifdef CONFIG_CMD_NAND
 static int splash_load_from_nand(u32 bmp_load_addr)
@@ -120,7 +95,23 @@ static inline int splash_load_from_nand(void)
 }
 #endif /* CONFIG_CMD_NAND */
 
-int board_splash_screen_prepare(void)
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+       timings->mr = MICRON_V_MR_165;
+       timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+       timings->ctrla = MICRON_V_ACTIMA_165;
+       timings->ctrlb = MICRON_V_ACTIMB_165;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
+int splash_screen_prepare(void)
 {
        char *env_splashimage_value;
        u32 bmp_load_addr;
@@ -147,9 +138,6 @@ int board_init(void)
 {
        gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 
-       enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
-                             CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
-
        /* board id for Linux */
        if (get_cpu_family() == CPU_OMAP34XX)
                gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
@@ -175,7 +163,7 @@ static u32 cm_t3x_rev;
 u32 get_board_rev(void)
 {
        if (!cm_t3x_rev)
-               cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
+               cm_t3x_rev = cl_eeprom_get_board_rev();
 
        return cm_t3x_rev;
 };
@@ -283,6 +271,9 @@ static void cm_t3x_set_common_muxconf(void)
        /* DVI enable */
        MUX_VAL(CP(GPMC_NCS3),          (IDIS  | PTU | DIS  | M4));/*GPMC_nCS3*/
 
+       /* DataImage backlight */
+       MUX_VAL(CP(GPMC_NCS7),          (IDIS  | PTU | DIS  | M4));/*GPIO_58*/
+
        /* CM-T3x Ethernet */
        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
        MUX_VAL(CP(GPMC_CLK),           (IEN  | PTD | DIS | M4)); /*GPIO_59*/
@@ -377,7 +368,7 @@ static void cm_t3x_set_common_muxconf(void)
        MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)); /*OFF_MODE*/
        MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)); /*CLKOUT1*/
        MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTU | DIS | M4)); /*green LED*/
-       MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
+       MUX_VAL(CP(JTAG_NTRST),         (IEN  | PTD | DIS | M0)); /*JTAG_NTRST*/
        MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
        MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
        MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
@@ -389,6 +380,15 @@ static void cm_t3x_set_common_muxconf(void)
        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
+
+       /* SPI */
+       MUX_VAL(CP(MCBSP1_CLKR),        (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+       MUX_VAL(CP(MCBSP1_DX),          (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+       MUX_VAL(CP(MCBSP1_DR),          (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+       MUX_VAL(CP(MCBSP1_FSX),         (IEN | PTU | EN  | M1)); /*MCSPI4_CS0*/
+
+       /* display controls */
+       MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | DIS | M4)); /*GPIO_157*/
 }
 
 static void cm_t35_set_muxconf(void)
@@ -443,7 +443,9 @@ void set_muxconf_regs(void)
                cm_t3730_set_muxconf();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_WP_GPIO 59
+
 int board_mmc_getcd(struct mmc *mmc)
 {
        u8 val;
@@ -456,7 +458,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-       return omap_mmc_init(0, 0, 0, -1, 59);
+       return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
 }
 #endif
 
@@ -485,7 +487,7 @@ static void setup_net_chip_gmpc(void)
                &ctrl_base->gpmc_nadv_ale);
 }
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
@@ -524,7 +526,7 @@ static int handle_mac_address(void)
        if (rc)
                return 0;
 
-       rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
+       rc = cl_eeprom_read_mac_addr(enetaddr);
        if (rc)
                return rc;
 
@@ -580,7 +582,8 @@ struct omap_usbhs_board_data usbhs_bdata = {
 };
 
 #define SB_T35_USB_HUB_RESET_GPIO      167
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+               struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        u8 val;
        int offset;
@@ -606,12 +609,11 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
        twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
        udelay(1);
 
-       return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+       return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(void)
 {
        return omap_ehci_hcd_stop();
 }
-
 #endif /* CONFIG_USB_EHCI_OMAP */