#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
* Miscelaneous platform dependent initialisations
*/
-static void at91sam9260ek_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
- at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
-#endif
-
-#ifdef CONFIG_USART1
- at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
-#endif
-
-#ifdef CONFIG_USART2
- at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-#endif
-}
-
#ifdef CONFIG_CMD_NAND
static void at91sam9260ek_nand_hw_init(void)
{
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PC13, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PC14, 1);
-}
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
-static void at91sam9260ek_spi_hw_init(void)
-{
- at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
- at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
-
- at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9260ek_macb_hw_init(void)
{
+ unsigned long rstc;
+
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0 << 8)) |
+ (rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
- at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK)
- /*
- * use PA10, PA11 for ETX2, ETX3.
- * PA23 and PA24 are for TWI EEPROM
- */
- at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
-#else
- at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
-#endif
- at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
-#endif
-
+ at91_macb_hw_init();
}
#endif
/* Enable Ctrlc */
console_init_f();
+#ifdef CONFIG_AT91SAM9G20EK
+ /* arch number of AT91SAM9260EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
+#else
/* arch number of AT91SAM9260EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
+#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- at91sam9260ek_serial_hw_init();
+ at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9260ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
- at91sam9260ek_spi_hw_init();
+ at91_spi0_hw_init((1 << 0) | (1 << 1));
#endif
#ifdef CONFIG_MACB
at91sam9260ek_macb_hw_init();
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
+ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
#endif
+ return rc;
}
-#endif
projects / platform / kernel / u-boot.git / blobdiff