/*
* (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*/
#include <common.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_CMD_NAND
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
#include <nand.h>
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
- AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+ at91_set_gpio_value(AT91_PIN_PD15, 1);
break;
case NAND_CTL_SETNCE:
- AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+ at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
+#ifdef CFG_NAND_DBW_16
+ nand->options = NAND_BUSWIDTH_16;
+#endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;
return 0;
}
-#endif