* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
+#include <command.h>
+#include <image.h>
+#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <bmp_logo.h>
-#include <pwm.h>
#include <dm/root.h>
#include <env.h>
+#include <env_internal.h>
+#include <i2c_eeprom.h>
+#include <i2c.h>
#include <micrel.h>
#include <miiphy.h>
#include <lcd.h>
#include <led.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/da9063_pmic.h>
#include <splash.h>
#include <video_fb.h>
DECLARE_GLOBAL_DATA_PTR;
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
enum {
BOARD_TYPE_4 = 4,
BOARD_TYPE_7 = 7,
#define ARI_BT_4 "aristainetos2_4@2"
#define ARI_BT_7 "aristainetos2_7@1"
-struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-struct i2c_pads_info i2c_pad_info4 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
- .gp = IMX_GPIO_NR(1, 7)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
- .gp = IMX_GPIO_NR(1, 8)
- }
-};
-
-static iomux_v3_cfg_t const backlight_pads[] = {
- /* backlight PWM brightness control */
- MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* backlight enable */
- MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LCD power enable */
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
int board_phy_config(struct phy_device *phydev)
{
/* control data pad skew - devaddr = 0x02, register = 0x04 */
writel(reg, &iomux->gpr[3]);
}
-static void enable_spi_display(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- s32 timeout = 100000;
-
-#if defined(CONFIG_VIDEO_BMP_LOGO)
- rotate_logo(3); /* portrait display in landscape mode */
-#endif
-
- reg = readl(&ccm->cs2cdr);
-
- /* select pll 5 clock */
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- writel(reg, &ccm->cs2cdr);
-
- /* set PLL5 to 197994996Hz */
- reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
- reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
- writel(reg, &ccm->analog_pll_video);
-
- writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
- &ccm->analog_pll_video_num);
- writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
- &ccm->analog_pll_video_denom);
-
- reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
- writel(reg, &ccm->analog_pll_video);
-
- while (timeout--)
- if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
- break;
- if (timeout < 0)
- printf("Warning: video pll lock timeout!\n");
-
- reg = readl(&ccm->analog_pll_video);
- reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
- reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
- writel(reg, &ccm->analog_pll_video);
-
- /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
- reg = readl(&ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &ccm->cs2cdr);
-
- reg = readl(&ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &ccm->cscmr2);
-
- reg = readl(&ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
- reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
- writel(reg, &ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
- | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-
static void setup_display(void)
{
enable_ipu_clock();
return 0;
}
-static void setup_i2c4(void)
-{
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- &i2c_pad_info4);
-}
-
static void setup_one_led(char *label, int state)
{
struct udevice *dev;
setup_one_led("led_blue", LEDST_OFF);
}
-int board_late_init(void)
+static void aristainetos_run_rescue_command(int reason)
{
+ char rescue_reason_command[20];
+
+ sprintf(rescue_reason_command, "setenv rreason %d", reason);
+ run_command(rescue_reason_command, 0);
+}
+
+static int aristainetos_bootmode_settings(void)
+{
+ struct gpio_desc *desc;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned int sbmr1 = readl(&psrc->sbmr1);
char *my_bootdelay;
char bootmode = 0;
- struct gpio_desc *desc;
- int x, y;
int ret;
+ struct udevice *dev;
+ int off;
+ u8 data[0x10];
+ u8 rescue_reason;
+
+ /* jumper controlled reset of the environment */
+ ret = gpio_hog_lookup_name("env_reset", &desc);
+ if (!ret) {
+ if (dm_gpio_get_value(desc)) {
+ printf("\nReset u-boot environment (jumper)\n");
+ run_command("run default_env; saveenv; saveenv", 0);
+ }
+ }
+
+ off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+ if (off < 0) {
+ printf("%s: No eeprom0 path offset\n", __func__);
+ return off;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+ if (ret) {
+ printf("%s: Could not find EEPROM\n", __func__);
+ return ret;
+ }
+
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret)
+ return ret;
+
+ ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
+ if (ret) {
+ printf("%s: Could not read EEPROM\n", __func__);
+ return ret;
+ }
+
+ /* software controlled reset of the environment (EEPROM magic) */
+ if (strncmp((char *)data, "DeF", 3) == 0) {
+ memset(data, 0xff, 3);
+ i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
+ printf("\nReset u-boot environment (EEPROM)\n");
+ run_command("run default_env; saveenv; saveenv", 0);
+ }
+
+ if (sbmr1 & 0x40) {
+ env_set("bootmode", "1");
+ printf("SD bootmode jumper set!\n");
+ } else {
+ env_set("bootmode", "0");
+ }
- led_default_state();
- splash_get_pos(&x, &y);
- bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
/*
* Check the boot-source. If booting from NOR Flash,
* disable bootdelay
*/
- desc = gpio_hog_lookup_name("bootsel0");
- if (desc)
+ ret = gpio_hog_lookup_name("bootsel0", &desc);
+ if (!ret)
bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
- desc = gpio_hog_lookup_name("bootsel1");
- if (desc)
+ ret = gpio_hog_lookup_name("bootsel1", &desc);
+ if (!ret)
bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
- desc = gpio_hog_lookup_name("bootsel2");
- if (desc)
+ ret = gpio_hog_lookup_name("bootsel2", &desc);
+ if (!ret)
bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
if (bootmode == 7) {
my_bootdelay = env_get("nor_bootdelay");
- if (my_bootdelay != NULL)
+ if (my_bootdelay)
env_set("bootdelay", my_bootdelay);
else
env_set("bootdelay", "-2");
}
- /* read out some jumper values*/
- ret = gpio_hog_lookup_name("env_reset", &desc);
- if (!ret) {
- if (dm_gpio_get_value(desc)) {
- printf("\nClear env (set back to defaults)\n");
- run_command("run default_env; saveenv; saveenv", 0);
- }
- }
+ /* jumper controlled boot of the rescue system */
ret = gpio_hog_lookup_name("boot_rescue", &desc);
if (!ret) {
if (dm_gpio_get_value(desc)) {
+ printf("\nBooting into Rescue System (jumper)\n");
aristainetos_run_rescue_command(16);
run_command("run rescue_xload_boot", 0);
}
}
+ /* software controlled boot of the rescue system (EEPROM magic) */
+ if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+ rescue_reason = *(uint8_t *)&data[9];
+ memset(&data[3], 0xff, 7);
+ i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+ printf("\nBooting into Rescue System (EEPROM)\n");
+ aristainetos_run_rescue_command(rescue_reason);
+ run_command("run rescue_xload_boot", 0);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_DM_PMIC_DA9063)
+/*
+ * On the aristainetos2c boards the PMIC needs to be initialized,
+ * because the Ethernet PHY uses a different regulator that is not
+ * setup per hardware default. This does not influence the other versions
+ * as this regulator isn't used there at all.
+ *
+ * Unfortunately we have not yet a interface to setup all
+ * values we need.
+ */
+static int setup_pmic_voltages(void)
+{
+ struct udevice *dev;
+ int off;
+ int ret;
+
+ off = fdt_path_offset(gd->fdt_blob, "pmic0");
+ if (off < 0) {
+ printf("%s: No pmic path offset\n", __func__);
+ return off;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
+ if (ret) {
+ printf("%s: Could not find PMIC\n", __func__);
+ return ret;
+ }
+
+ pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
+ pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
+ ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
+ if (ret < 0) {
+ printf("%s: error %d get register\n", __func__, ret);
+ return ret;
+ }
+ ret &= 0xf0;
+ ret |= 0x09;
+ pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
+ pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
+ pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
+
+ return 0;
+}
+#else
+static int setup_pmic_voltages(void)
+{
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+ int x, y;
+ int ret;
+
+ led_default_state();
+ splash_get_pos(&x, &y);
+ bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
+
+ ret = aristainetos_bootmode_settings();
+ if (ret)
+ return ret;
+
/* set board_type */
if (gd->board_type == BOARD_TYPE_4)
env_set("board_type", ARI_BT_4);
else
env_set("board_type", ARI_BT_7);
+ if (setup_pmic_voltages())
+ printf("Error setup PMIC\n");
+
return 0;
}
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
.vmode = FB_VMODE_NONINTERLACED
}
}
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
- , {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_spi_display,
- .mode = {
- .name = "lg4573",
- .refresh = 57,
- .xres = 480,
- .yres = 800,
- .pixclock = 37037,
- .left_margin = 59,
- .right_margin = 10,
- .upper_margin = 15,
- .lower_margin = 15,
- .hsync_len = 10,
- .vsync_len = 15,
- .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED
- }
- }
-#endif
};
size_t display_count = ARRAY_SIZE(displays);
-iomux_v3_cfg_t nfc_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nfc_pads,
- ARRAY_SIZE(nfc_pads));
-
- /* gate ENFC_CLK_ROOT clock first,before clk source switch */
- clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable ENFC_CLK_ROOT clock */
- setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-
int board_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- &i2c_pad_info1);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- &i2c_pad_info2);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- &i2c_pad_info3);
- setup_i2c4();
-
setup_board_gpio();
- setup_gpmi_nand();
setup_display();
/* GPIO_1 for USB_OTG_ID */
return 0;
}
-int checkboard(void)
-{
- printf("Board: %s\n", CONFIG_BOARDNAME);
- return 0;
-}
-
int board_fit_config_name_match(const char *name)
{
if (gd->board_type == BOARD_TYPE_4 &&
return 0;
}
#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+ return ENVL_SPI_FLASH;
+
+ switch (prio) {
+ case 0:
+ return ENVL_NOWHERE;
+
+ case 1:
+ return ENVL_SPI_FLASH;
+
+ default:
+ return ENVL_UNKNOWN;
+ }
+
+ return ENVL_UNKNOWN;
+}
projects / platform / kernel / u-boot.git / blobdiff