rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / apollon / mem.h

diff --git a/board/apollon/mem.h b/board/apollon/mem.h
index aed7e1d..09c4ea4 100644 (file)
--- a/board/apollon/mem.h
+++ b/board/apollon/mem.h
@@ -44,15 +44,15 @@
 #define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz    0x00000506
 
 #ifdef PRCM_CONFIG_I
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0       APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0       APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
-# define APOLLON_2420_SDRC_RFR_CTRL            APOLLON_242X_SDRC_RFR_CTRL_166MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL          APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0        APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0        APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+#define APOLLON_2420_SDRC_RFR_CTRL     APOLLON_242X_SDRC_RFR_CTRL_166MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL   APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
 #elif PRCM_CONFIG_II
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0       APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0       APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define APOLLON_2420_SDRC_RFR_CTRL            APOLLON_242X_SDRC_RFR_CTRL_100MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL          APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0        APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0        APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+#define APOLLON_2420_SDRC_RFR_CTRL     APOLLON_242X_SDRC_RFR_CTRL_100MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL   APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
 #endif
 
 /* GPMC settings */
@@ -67,7 +67,7 @@
 # define APOLLON_24XX_GPMC_CONFIG7_0   (0x00000e40|(APOLLON_CS0_BASE >> 24))
 
 /* CS1: Ethernet */
-# define APOLLON_24XX_GPMC_CONFIG1_1   0x00011200
+# define APOLLON_24XX_GPMC_CONFIG1_1   0x00011203
 # define APOLLON_24XX_GPMC_CONFIG2_1   0x001F1F01
 # define APOLLON_24XX_GPMC_CONFIG3_1   0x00080803
 # define APOLLON_24XX_GPMC_CONFIG4_1   0x1C0b1C0a
@@ -142,7 +142,7 @@
 #endif /* endif PRCM_CONFIG_II */
 
 #ifdef PRCM_CONFIG_III         /* L3 at 133MHz */
-# ifdef CFG_NAND_BOOT
+# ifdef CONFIG_SYS_NAND_BOOT
 #  define APOLLON_24XX_GPMC_CONFIG1_0   0x0
 #  define APOLLON_24XX_GPMC_CONFIG2_0   0x00141400
 #  define APOLLON_24XX_GPMC_CONFIG3_0   0x00141400
@@ -156,7 +156,7 @@
 #  define APOLLON_24XX_GPMC_CONFIG4_0   0x10081008
 #  define APOLLON_24XX_GPMC_CONFIG5_0   0x01131F1F
 #  define APOLLON_24XX_GPMC_CONFIG6_0   0x000004c4
-# endif        /* endif CFG_NAND_BOOT */
+# endif        /* endif CONFIG_SYS_NAND_BOOT */
 # define APOLLON_24XX_GPMC_CONFIG7_0   (0x00000C40|(APOLLON_CS0_BASE >> 24))
 # define APOLLON_24XX_GPMC_CONFIG1_1   0x00011000
 # define APOLLON_24XX_GPMC_CONFIG2_1   0x001f1f01
@@ -165,6 +165,6 @@
 # define APOLLON_24XX_GPMC_CONFIG5_1   0x041f1F1F
 # define APOLLON_24XX_GPMC_CONFIG6_1   0x000004C4
 # define APOLLON_24XX_GPMC_CONFIG7_1   (0x00000F40|(APOLLON_CS1_BASE >> 24))
-#endif /* endif CFG_PRCM_III */
+#endif /* endif CONFIG_SYS_PRCM_III */
 
 #endif /* endif _APOLLON_OMAP24XX_MEM_H_ */