Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / board / amcc / yucca / yucca.c

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 52486cc..84c3938 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) {
        return default_val;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-       uint *pstart = (uint *) 0x00000000;
-       uint *pend = (uint *) 0x08000000;
-       uint *p;
-
-       for (p = pstart; p < pend; p++)
-               *p = 0xaaaaaaaa;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0xaaaaaaaa) {
-                       printf ("SDRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-
-       for (p = pstart; p < pend; p++)
-               *p = 0x55555555;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0x55555555) {
-                       printf ("SDRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-       return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
@@ -707,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
        return 1;
 }
 
-int yucca_pcie_card_present(int port)
+static int yucca_pcie_card_present(int port)
 {
        u16 reg;
 
@@ -737,27 +707,27 @@ void yucca_setup_pcie_fpga_rootpoint(int port)
        case 0:
                rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
                endpoint    = 0;
-               power       = FPGA_REG1A_PE0_PWRON;
+               power       = FPGA_REG1A_PE0_PWRON;
                green_led   = FPGA_REG1A_PE0_GLED;
-               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE0_YLED;
                reset_off   = FPGA_REG1C_PE0_PERST;
                break;
        case 1:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-               power       = FPGA_REG1A_PE1_PWRON;
+               power       = FPGA_REG1A_PE1_PWRON;
                green_led   = FPGA_REG1A_PE1_GLED;
-               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE1_YLED;
                reset_off   = FPGA_REG1C_PE1_PERST;
                break;
        case 2:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-               power       = FPGA_REG1A_PE2_PWRON;
+               power       = FPGA_REG1A_PE2_PWRON;
                green_led   = FPGA_REG1A_PE2_GLED;
-               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE2_YLED;
                reset_off   = FPGA_REG1C_PE2_PERST;
                break;
@@ -794,27 +764,27 @@ void yucca_setup_pcie_fpga_endpoint(int port)
        case 0:
                rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
                endpoint    = 0;
-               power       = FPGA_REG1A_PE0_PWRON;
+               power       = FPGA_REG1A_PE0_PWRON;
                green_led   = FPGA_REG1A_PE0_GLED;
-               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE0_YLED;
                reset_off   = FPGA_REG1C_PE0_PERST;
                break;
        case 1:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-               power       = FPGA_REG1A_PE1_PWRON;
+               power       = FPGA_REG1A_PE1_PWRON;
                green_led   = FPGA_REG1A_PE1_GLED;
-               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE1_YLED;
                reset_off   = FPGA_REG1C_PE1_PERST;
                break;
        case 2:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-               power       = FPGA_REG1A_PE2_PWRON;
+               power       = FPGA_REG1A_PE2_PWRON;
                green_led   = FPGA_REG1A_PE2_GLED;
-               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE2_YLED;
                reset_off   = FPGA_REG1C_PE2_PERST;
                break;
@@ -884,21 +854,21 @@ void pcie_setup_hoses(int busno)
                        /*
                         * Reson for no scanning is endpoint can not generate
                         * upstream configuration accesses.
-                        */
+                        */
                } else {
                        ppc4xx_setup_pcie_rootpoint(hose, i);
                        env = getenv("pciscandelay");
                        if (env != NULL) {
                                delay = simple_strtoul(env, NULL, 10);
                                if (delay > 5)
-                                       printf("Warning, expect noticable delay before "
+                                       printf("Warning, expect noticable delay before "
                                               "PCIe scan due to 'pciscandelay' value!\n");
                                mdelay(delay * 1000);
                        }
 
                        /*
                         * Config access can only go down stream
-                        */
+                        */
                        hose->last_busno = pci_hose_scan(hose);
                        bus = hose->last_busno + 1;
                }
@@ -909,10 +879,6 @@ void pcie_setup_hoses(int busno)
 int misc_init_f (void)
 {
        uint reg;
-#if defined(CONFIG_STRESS)
-       uint i ;
-       uint disp;
-#endif
 
        out16(FPGA_REG10, (in16(FPGA_REG10) &
                        ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@@ -927,67 +893,23 @@ int misc_init_f (void)
 
        /* minimal init for PCIe */
        /* pci express 0 Endpoint Mode */
-       mfsdr(SDR0_PE0DLPSET, reg);
+       mfsdr(SDRN_PESDR_DLPSET(0), reg);
        reg &= (~0x00400000);
-       mtsdr(SDR0_PE0DLPSET, reg);
+       mtsdr(SDRN_PESDR_DLPSET(0), reg);
        /* pci express 1 Rootpoint  Mode */
-       mfsdr(SDR0_PE1DLPSET, reg);
+       mfsdr(SDRN_PESDR_DLPSET(1), reg);
        reg |= 0x00400000;
-       mtsdr(SDR0_PE1DLPSET, reg);
+       mtsdr(SDRN_PESDR_DLPSET(1), reg);
        /* pci express 2 Rootpoint  Mode */
-       mfsdr(SDR0_PE2DLPSET, reg);
+       mfsdr(SDRN_PESDR_DLPSET(2), reg);
        reg |= 0x00400000;
-       mtsdr(SDR0_PE2DLPSET, reg);
+       mtsdr(SDRN_PESDR_DLPSET(2), reg);
 
        out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
                                ~FPGA_REG1C_PE0_ROOTPOINT &
                                ~FPGA_REG1C_PE1_ENDPOINT  &
                                ~FPGA_REG1C_PE2_ENDPOINT));
 
-#if defined(CONFIG_STRESS)
-       /*
-        * all this setting done by linux only needed by stress an charac. test
-        * procedure
-        * PCIe 1 Rootpoint PCIe2 Endpoint
-        * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-        * Power Level
-        */
-       for (i = 0, disp = 0; i < 8; i++, disp += 3) {
-               mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-               reg |= 0x33000000;
-               mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-       }
-
-       /*
-        * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-        * Power Level
-        */
-       for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-               mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-               reg |= 0x33000000;
-               mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-       }
-
-       /*
-        * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-        * Power Level
-        */
-       for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-               mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-               reg |= 0x33000000;
-               mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-       }
-
-       reg = 0x21242222;
-       mtsdr(SDR0_PE2UTLSET1, reg);
-       reg = 0x11000000;
-       mtsdr(SDR0_PE2UTLSET2, reg);
-       /* pci express 1 Endpoint  Mode */
-       reg = 0x00004000;
-       mtsdr(SDR0_PE2DLPSET, reg);
-
-       mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
-#endif
        return 0;
 }