ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / amcc / yucca / yucca.c

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index e0c1268..245004c 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -167,7 +167,7 @@ int board_early_init_f (void)
         |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
         |
         +-------------------------------------------------------------------*/
-       mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+       mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
                        EBC_CFG_PTD_ENABLE |
                        EBC_CFG_RTC_16PERCLK |
                        EBC_CFG_ATC_PREVIOUS |
@@ -188,8 +188,8 @@ int board_early_init_f (void)
         | boot type
         |
         +-------------------------------------------------------------------*/
-       mtebc(pb1ap, EBC_BXAP_FPGA);
-       mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
+       mtebc(PB1AP, EBC_BXAP_FPGA);
+       mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
 
        /*-------------------------------------------------------------------+
         |
@@ -334,10 +334,10 @@ int board_early_init_f (void)
                        break;
        }
 
-       mtebc(pb0ap, ebc0_cs0_bxap_value);
-       mtebc(pb0cr, ebc0_cs0_bxcr_value);
-       mtebc(pb2ap, ebc0_cs2_bxap_value);
-       mtebc(pb2cr, ebc0_cs2_bxcr_value);
+       mtebc(PB0AP, ebc0_cs0_bxap_value);
+       mtebc(PB0CR, ebc0_cs0_bxcr_value);
+       mtebc(PB2AP, ebc0_cs2_bxap_value);
+       mtebc(PB2CR, ebc0_cs2_bxcr_value);
 
        /*--------------------------------------------------------------------+
         | Interrupt controller setup for the AMCC 440SPe Evaluation board.
@@ -530,9 +530,9 @@ int board_early_init_f (void)
        mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
        mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 
-       mfsdr(sdr_mfr, mfr);
+       mfsdr(SDR0_MFR, mfr);
        mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
-       mtsdr(sdr_mfr, mfr);
+       mtsdr(SDR0_MFR, mfr);
 
        fpga_init();
 
@@ -608,7 +608,7 @@ int pci_pre_init(struct pci_controller * hose )
         *      The yucca board is always configured as the host & requires the
         *      PCI arbiter to be enabled.
         *-------------------------------------------------------------------*/
-       mfsdr(sdr_sdstp1, strap);
+       mfsdr(SDR0_SDSTP1, strap);
        if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
                printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
                return 0;
@@ -626,7 +626,7 @@ int pci_pre_init(struct pci_controller * hose )
  *     may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
        /*-------------------------------------------------------------------+
@@ -641,7 +641,7 @@ void pci_target_init(struct pci_controller * hose )
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
        out32r( PCIX0_PIM0LAH, 0 );
        out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
        out32r( PCIX0_BAR0, 0 );
@@ -649,12 +649,12 @@ void pci_target_init(struct pci_controller * hose )
        /*-------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
        out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 #if defined(CONFIG_PCI)
 /*************************************************************************
@@ -843,9 +843,9 @@ void pcie_setup_hoses(int busno)
 
                /* setup mem resource */
                pci_set_region(hose->regions + 0,
-                       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                       CFG_PCIE_MEMSIZE,
+                       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                       CONFIG_SYS_PCIE_MEMSIZE,
                        PCI_REGION_MEM);
                hose->region_count = 1;
                pci_register_hose(hose);
@@ -956,5 +956,6 @@ int onboard_pci_arbiter_selected(int core_pci)
 
 int board_eth_init(bd_t *bis)
 {
+       cpu_eth_init(bis);
        return pci_eth_init(bis);
 }