#include <asm/processor.h>
#include <asm/io.h>
#include <spi.h>
-#include <asm/gpio.h>
+#include <netdev.h>
+#include <asm/ppc4xx-gpio.h>
extern int lcd_init(void);
{
lcd_init();
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000);
- mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
- mtdcr(uictr, 0x00000000); /* set int trigger levels */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000);
+ mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
- mtebc(pb3cr, CFG_EBC_PB3CR);
+ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
+ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter
+ */
+ mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
return 0;
}
return 0;
}
-/*************************************************************************
- * long int initdram
- *
- ************************************************************************/
-long int initdram(int board)
-{
- return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
-}
-
-static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
{
char stat;
int i;
U_BOOT_CMD (
sw2_stat, 1, 1, do_sw_stat,
- "sw2_stat - show status of switch 2\n",
- NULL
- );
+ "show status of switch 2",
+ ""
+);
-static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
{
int led_no;
- if (argc != 3) {
- printf("%s", cmd_tp->usage);
- return -1;
- }
+ if (argc != 3)
+ return cmd_usage(cmd_tp);
led_no = simple_strtoul(argv[1], NULL, 16);
- if (led_no != 1 && led_no != 2) {
- printf("%s", cmd_tp->usage);
- return -1;
- }
+ if (led_no != 1 && led_no != 2)
+ return cmd_usage(cmd_tp);
if (strcmp(argv[2],"off") == 0x0) {
if (led_no == 1)
else
gpio_write_bit(31, 0);
} else {
- printf("%s", cmd_tp->usage);
- return -1;
+ return cmd_usage(cmd_tp);
}
return 0;
U_BOOT_CMD (
led_ctl, 3, 1, do_led_ctl,
- "led_ctl - make led 1 or 2 on or off\n",
+ "make led 1 or 2 on or off",
"<led_no> <on/off> - make led <led_no> on/off,\n"
- "\tled_no is 1 or 2\t"
- );
+ "\tled_no is 1 or 2"
+);
#define SPI_CS_GPIO0 0
#define SPI_SCLK_GPIO14 14
unsigned char spi_read(void)
{
- return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+ return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
}
-void taihu_spi_chipsel(int cs)
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- gpio_write_bit(SPI_CS_GPIO0, cs);
+ return bus == 0 && cs == 0;
}
-spi_chipsel_type spi_chipsel[]= {
- taihu_spi_chipsel
-};
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_write_bit(SPI_CS_GPIO0, 1);
+}
-int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_write_bit(SPI_CS_GPIO0, 0);
+}
#ifdef CONFIG_PCI
static unsigned char int_lines[32] = {
}
#endif /* CONFIG_PCI */
-#ifdef CFG_DRAM_TEST
-int testdram(void)
+int board_eth_init(bd_t *bis)
{
- unsigned long *mem = (unsigned long *)0;
- const unsigned long kend = (1024 / sizeof(unsigned long));
- unsigned long k, n;
- unsigned long msr;
- unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_EE));
-
- for (k = 0; k < total_kbytes ;
- ++k, mem += (1024 / sizeof(unsigned long))) {
- if ((k & 1023) == 0)
- printf("%3d MB\r", k / 1024);
-
- memset(mem, 0xaaaaaaaa, 1024);
- for (n = 0; n < kend; ++n) {
- if (mem[n] != 0xaaaaaaaa) {
- printf("SDRAM test fails at: %08x\n",
- (uint) & mem[n]);
- return 1;
- }
- }
-
- memset(mem, 0x55555555, 1024);
- for (n = 0; n < kend; ++n) {
- if (mem[n] != 0x55555555) {
- printf("SDRAM test fails at: %08x\n",
- (uint) & mem[n]);
- return 1;
- }
- }
- }
- printf("SDRAM test passes\n");
- mtmsr(msr);
-
- return 0;
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
}
-#endif /* CFG_DRAM_TEST */