/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#if !defined(CONFIG_SYS_NO_FLASH)
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#endif
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+ulong flash_get_size(ulong base, int banknum);
-ulong flash_get_size (ulong base, int banknum);
+static inline u32 get_async_pci_freq(void)
+{
+ if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+ CONFIG_SYS_BCSR5_PCI66EN)
+ return 66666666;
+ else
+ return 33333333;
+}
int board_early_init_f(void)
{
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
- mtdcr(ebccfga, xbcfg);
- mtdcr(ebccfgd, 0xb8400000);
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
- mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- mtdcr(uic2sr, 0xffffffff); /* clear all */
- mtdcr(uic2er, 0x00000000); /* disable all */
- mtdcr(uic2cr, 0x00000000); /* all non-critical */
- mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* Check and reconfigure the PCI sync clock if necessary */
+ ppc4xx_pci_sync_clock_config(get_async_pci_freq());
/* 50MHz tmrclk */
- out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
/* clear write protects */
- out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
/* enable Ethernet */
- out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
/* enable USB device */
- out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
/* select Ethernet (and optionally IIC1) pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
#ifdef CONFIG_I2C_MULTI_BUS
sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
#endif
+ /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
+
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg);
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CFG_NAND_CS));
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
int misc_init_r(void)
{
+#if !defined(CONFIG_SYS_NO_FLASH)
uint pbcr;
int size_val = 0;
- u32 reg;
+#endif
#ifdef CONFIG_440EPX
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
char *act = getenv("usbact");
#endif
+ u32 reg;
+#if !defined(CONFIG_SYS_NO_FLASH)
/* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(ebccfga, pb3cr);
+ mtdcr(EBC0_CFGADDR, PB3CR);
#else
- mtdcr(ebccfga, pb0cr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
#endif
- pbcr = mfdcr(ebccfgd);
+ pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(ebccfga, pb3cr);
+ mtdcr(EBC0_CFGADDR, PB3CR);
#else
- mtdcr(ebccfga, pb0cr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
#endif
- mtdcr(ebccfgd, pbcr);
+ mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
+#endif /* CONFIG_SYS_NO_FLASH */
/*
* USB suff...
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
- reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
- mtdcr(plb4_acr, reg);
+ reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
+ mtdcr(PLB4_ACR, reg);
return 0;
}
{
char *s = getenv("serial#");
u8 rev;
- u8 val;
+ u32 clock = get_async_pci_freq();
#ifdef CONFIG_440EPX
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
- rev = in_8((void *)(CFG_BCSR_BASE + 0));
- val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
- printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+ rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+ printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
if (s != NULL) {
puts(", serial# ");
}
putc('\n');
+ /*
+ * Reconfiguration of the PCI sync clock is already done,
+ * now check again if everything is in range:
+ */
+ if (ppc4xx_pci_sync_clock_config(clock)) {
+ printf("ERROR: PCI clocking incorrect (async=%d "
+ "sync=%ld)!\n", clock, get_PCI_freq());
+ }
+
return (0);
}
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
- mfsdr(sdr_amp1, addr);
- mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb3_acr);
- mtdcr(plb3_acr, addr | 0x80000000);
+ mfsdr(SD0_AMP1, addr);
+ mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB3_ACR);
+ mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
- mfsdr(sdr_amp0, addr);
- mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
- mtdcr(plb4_acr, addr);
+ mfsdr(SD0_AMP0, addr);
+ mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
- addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
- addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
- addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
- addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
- mtdcr(plb0_acr, addr);
+ addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+ addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+ mtdcr(PLB0_ACR, addr);
/* Segment1 */
- addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
- addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
- addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
- addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
- mtdcr(plb1_acr, addr);
+ addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+ addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+ mtdcr(PLB1_ACR, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = sequoia_pci_fixup_irq;
}
#endif /* defined(CONFIG_PCI) */
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CFG_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Cactus is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
#if defined(CONFIG_POST)
/*
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+/*
+ * On NAND-booting sequoia, we need to patch the chips select numbers
+ * in the dtb (CS0 - NAND, CS3 - NOR)
+ */
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+ int len;
+ int nodeoffset;
+ struct fdt_property *prop;
+ u32 *reg;
+ char path[32];
+
+ /* First do common fdt setup */
+ __ft_board_setup(blob, bd);
+
+ /* And now configure NOR chip select to 3 instead of 0 */
+ strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NOR chip select for NAND booting\n");
+ return;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 3;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NOR mappings, err=%s\n",
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* And now configure NAND chip select to 0 instead of 3 */
+ strcpy(path, "/plb/opb/ebc/ndfc@3,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NDFC chip select for NAND booting\n");
+ return;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 0;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NDFC mappings, err=%s\n",
+ fdt_strerror(rc));
+ return;
+ }
+}
+#endif /* CONFIG_NAND_U_BOOT */
projects / platform / kernel / u-boot.git / blobdiff