* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* define DEBUG for debug output */
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <ppc440.h>
+#include <asm/ppc440.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/*-----------------------------------------------------------------------------+
* Prototypes
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
-#if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val) 133000000
-#endif
-
/*************************************************************************
*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+int dram_init(void)
{
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#if !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
-#else
- ulong speed = 133333333; /* 133MHz is on the safe side */
-#endif
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_07, 0x000D0100);
mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000300);
+ mtsdram(DDR0_10, 0x00000100);
mtsdram(DDR0_11, 0x0027C800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
denali_core_search_data_eye();
#endif
- return (CFG_MBYTES_SDRAM << 20);
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}