Merge with /home/stefan/git/u-boot/bamboo-nand

[platform/kernel/u-boot.git] / board / amcc / sequoia / sdram.c

diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 77f1438..78e2cb4 100644 (file)
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -6,7 +6,7 @@
  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  *
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
 }
 #endif /* CONFIG_DDR_DATA_EYE */
 
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val)      133000000
+#endif
+
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -379,16 +387,22 @@ void denali_core_search_data_eye(unsigned long memory_size)
 long int initdram (int board_type)
 {
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_SPL)
+       ulong speed = get_bus_freq(0);
+#else
+       ulong speed = 133333333;        /* 133MHz is on the safe side   */
+#endif
+
        mtsdram(DDR0_02, 0x00000000);
 
        mtsdram(DDR0_00, 0x0000190A);
        mtsdram(DDR0_01, 0x01000000);
        mtsdram(DDR0_03, 0x02030602);
-       mtsdram(DDR0_04, 0x13030300);
-       mtsdram(DDR0_05, 0x0202050E);
-       mtsdram(DDR0_06, 0x0104C823);
+       mtsdram(DDR0_04, 0x0A020200);
+       mtsdram(DDR0_05, 0x02020308);
+       mtsdram(DDR0_06, 0x0102C812);
        mtsdram(DDR0_07, 0x000D0100);
-       mtsdram(DDR0_08, 0x02360001);
+       mtsdram(DDR0_08, 0x02430001);
        mtsdram(DDR0_09, 0x00011D5F);
        mtsdram(DDR0_10, 0x00000300);
        mtsdram(DDR0_11, 0x0027C800);
@@ -402,13 +416,16 @@ long int initdram (int board_type)
        mtsdram(DDR0_22, 0x00267F0B);
        mtsdram(DDR0_23, 0x00000000);
        mtsdram(DDR0_24, 0x01010002);
-       mtsdram(DDR0_26, 0x5B260181);
+       if (speed > 133333334)
+               mtsdram(DDR0_26, 0x5B26050C);
+       else
+               mtsdram(DDR0_26, 0x5B260408);
        mtsdram(DDR0_27, 0x0000682B);
        mtsdram(DDR0_28, 0x00000000);
        mtsdram(DDR0_31, 0x00000000);
        mtsdram(DDR0_42, 0x01000006);
-       mtsdram(DDR0_43, 0x050A0200);
-       mtsdram(DDR0_44, 0x00000005);
+       mtsdram(DDR0_43, 0x030A0200);
+       mtsdram(DDR0_44, 0x00000003);
        mtsdram(DDR0_02, 0x00000001);
 
        wait_for_dlllock();