#include <asm/gpio.h>
#include <asm/io.h>
#include <fdt_support.h>
+#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Board early initialization function
| interrupts again.
+-------------------------------------------------------------------*/
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts */
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic1er, 0x00000000); /* disable all interrupts */
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
- mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
mtsdr(SDR0_SRST, 0);
/* Reset PCIe slots */
- gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
udelay(100);
- gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
/*
* Configure PFC (Pin Function Control) registers
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
#endif
}
#endif /* defined(CONFIG_PCI) */
-#ifdef CONFIG_PCI
-static struct pci_controller pcie_hose[2] = {{0},{0}};
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- bus = busno;
- char *env;
- unsigned int delay;
-
- for (i = 0; i < 2; i++) {
-
- if (is_end_point(i))
- ret = ppc4xx_init_pcie_endport(i);
- else
- ret = ppc4xx_init_pcie_rootport(i);
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
-}
-#endif
-
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
projects / platform / kernel / u-boot.git / blobdiff