ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / amcc / luan / luan.c

diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index b28ebf9..71ad89f 100644 (file)
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -25,6 +25,7 @@
 #include <command.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
 #include <spd_sdram.h>
 #include "epld.h"
 
@@ -41,12 +42,12 @@ int board_early_init_f(void)
 {
        u32 mfr;
 
-       mtebc( pb0ap,  0x03800000 );    /* set chip selects */
-       mtebc( pb0cr,  0xffc58000 );    /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
-       mtebc( pb1ap,  0x03800000 );
-       mtebc( pb1cr,  0xff018000 );    /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
-       mtebc( pb2ap,  0x03800000 );
-       mtebc( pb2cr,  0xff838000 );    /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+       mtebc( PB0AP,  0x03800000 );    /* set chip selects */
+       mtebc( PB0CR,  0xffc58000 );    /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+       mtebc( PB1AP,  0x03800000 );
+       mtebc( PB1CR,  0xff018000 );    /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+       mtebc( PB2AP,  0x03800000 );
+       mtebc( PB2CR,  0xff838000 );    /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
 
        mtdcr( uic1sr, 0xffffffff );    /* Clear all interrupts */
        mtdcr( uic1er, 0x00000000 );    /* disable all interrupts */
@@ -66,9 +67,9 @@ int board_early_init_f(void)
        mtdcr( uic0sr, 0x00000000 );    /* clear all interrupts */
        mtdcr( uic0sr, 0xffffffff );
 
-       mfsdr(sdr_mfr, mfr);
+       mfsdr(SDR0_MFR, mfr);
        mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
-       mtsdr(sdr_mfr, mfr);
+       mtsdr(SDR0_MFR, mfr);
 
        return  0;
 }
@@ -146,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose )
         *      The luan board is always configured as the host & requires the
         *      PCI arbiter to be enabled.
         *--------------------------------------------------------------------------*/
-       mfsdr(sdr_sdstp1, strap);
+       mfsdr(SDR0_SDSTP1, strap);
        if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
                printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 
@@ -255,7 +256,7 @@ static int on_off( const char *s )
  ************************************************************************/
 static void l2cache_disable(void)
 {
-       mtdcr( l2_cache_cfg, 0 );
+       mtdcr( L2_CACHE_CFG, 0 );
 }
 
 
@@ -265,24 +266,24 @@ static void l2cache_disable(void)
  ************************************************************************/
 static void l2cache_enable(void)       /* see p258 7.4.1 Enabling L2 Cache */
 {
-       mtdcr( l2_cache_cfg, 0x80000000 );      /* enable L2_MODE L2_CFG[L2M] */
+       mtdcr( L2_CACHE_CFG, 0x80000000 );      /* enable L2_MODE L2_CFG[L2M] */
 
-       mtdcr( l2_cache_addr, 0 );              /* set L2_ADDR with all zeros */
+       mtdcr( L2_CACHE_ADDR, 0 );              /* set L2_ADDR with all zeros */
 
-       mtdcr( l2_cache_cmd, 0x80000000 );      /* issue HCLEAR command via L2_CMD */
+       mtdcr( L2_CACHE_CMD, 0x80000000 );      /* issue HCLEAR command via L2_CMD */
 
-       while (!(mfdcr( l2_cache_stat ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
+       while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
 
-       mtdcr( l2_cache_cmd, 0x10000000 );      /* clear cache errors L2_CMD[CCP] */
+       mtdcr( L2_CACHE_CMD, 0x10000000 );      /* clear cache errors L2_CMD[CCP] */
 
-       mtdcr( l2_cache_cmd, 0x08000000 );      /* clear tag errors L2_CMD[CTE] */
+       mtdcr( L2_CACHE_CMD, 0x08000000 );      /* clear tag errors L2_CMD[CTE] */
 
-       mtdcr( l2_cache_snp0, 0 );              /* snoop registers */
-       mtdcr( l2_cache_snp1, 0 );
+       mtdcr( L2_CACHE_SNP0, 0 );              /* snoop registers */
+       mtdcr( L2_CACHE_SNP1, 0 );
 
        __asm__ volatile ("sync");              /* msync */
 
-       mtdcr( l2_cache_cfg, 0xe0000000 );      /* inst and data use L2 */
+       mtdcr( L2_CACHE_CFG, 0xe0000000 );      /* inst and data use L2 */
 
        __asm__ volatile ("sync");
 }
@@ -294,7 +295,7 @@ static void l2cache_enable(void)    /* see p258 7.4.1 Enabling L2 Cache */
  ************************************************************************/
 static int l2cache_status(void)
 {
-       return  (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+       return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
 }
 
 
@@ -318,7 +319,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
                        l2cache_status() ? "ON" : "OFF");
                return 0;
        default:
-               printf ("Usage:\n%s\n", cmdtp->usage);
+               cmd_usage(cmdtp);
                return 1;
        }
 
@@ -328,7 +329,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 
 U_BOOT_CMD(
        l2cache,   2,   1,     do_l2cache,
-       "l2cache  - enable or disable L2 cache\n",
+       "enable or disable L2 cache",
        "[on, off]\n"
-       "    - enable or disable L2 cache\n"
-       );
+       "    - enable or disable L2 cache"
+);