#include <ppc4xx.h>
#include <ppc405.h>
#include <libfdt.h>
+#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-void fpga_init(void)
-{
- /*
- * Set FPGA regs
- */
- out32(CFG_FPGA_BASE, 0xff570cc0);
-}
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Board early initialization function
*/
mtsdr(SDR0_SRST, 0);
- fpga_init();
-
/* Configure 405EX for NAND usage */
val = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NRB_BUSY |
- (0x80000000 >> (28 + CFG_NAND_CS));
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, val);
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
+
return 0;
}
int misc_init_r(void)
{
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
#endif
return 0;
}
-int board_emac_count(void)
+static int is_405exr(void)
{
u32 pvr = get_pvr();
+ if (pvr & 0x00000004)
+ return 0; /* bit 2 set -> 405EX */
+
+ return 1; /* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
return 1;
else
return 2;
static int board_pcie_count(void)
{
- u32 pvr = get_pvr();
-
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
return 1;
else
return 2;
int checkboard (void)
{
char *s = getenv("serial#");
- u32 pvr = get_pvr();
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
else
printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIX0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
#ifdef CONFIG_PCI
static struct pci_controller pcie_hose[2] = {{0},{0}};
/* setup mem resource */
pci_set_region(hose->regions + 0,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMSIZE,
+ CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+ CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+ CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
+ ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
- */
+ */
} else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
+ ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
- printf("Warning, expect noticable delay before "
+ printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
}
}
}
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- u32 val[4];
- int rc;
-
- ft_cpu_setup(blob, bd);
-
- /* Fixup NOR mapping */
- val[0] = 0; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
- val[3] = gd->bd->bi_flashsize;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc)
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
projects / platform / kernel / u-boot.git / blobdiff