ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / amcc / ebony / ebony.c

diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index c6375ac..2439b03 100644 (file)
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -35,36 +35,36 @@ long int fixed_sdram(void);
 int board_early_init_f(void)
 {
        uint reg;
-       unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+       unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
        unsigned char status;
 
        /*--------------------------------------------------------------------
         * Setup the external bus controller/chip selects
         *-------------------------------------------------------------------*/
-       mtdcr(ebccfga, xbcfg);
-       reg = mfdcr(ebccfgd);
-       mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
+       mtdcr(EBC0_CFGADDR, EBC0_CFG);
+       reg = mfdcr(EBC0_CFGDATA);
+       mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
 
-       mtebc(pb1ap, 0x02815480);       /* NVRAM/RTC */
-       mtebc(pb1cr, 0x48018000);       /* BA=0x480 1MB R/W 8-bit */
-       mtebc(pb7ap, 0x01015280);       /* FPGA registers */
-       mtebc(pb7cr, 0x48318000);       /* BA=0x483 1MB R/W 8-bit */
+       mtebc(PB1AP, 0x02815480);       /* NVRAM/RTC */
+       mtebc(PB1CR, 0x48018000);       /* BA=0x480 1MB R/W 8-bit */
+       mtebc(PB7AP, 0x01015280);       /* FPGA registers */
+       mtebc(PB7CR, 0x48318000);       /* BA=0x483 1MB R/W 8-bit */
 
        /* read FPGA_REG0  and set the bus controller */
        status = *fpga_base;
        if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
-               mtebc(pb0ap, 0x9b015480);       /* FLASH/SRAM */
-               mtebc(pb0cr, 0xfff18000);       /* BAS=0xfff 1MB R/W 8-bit */
-               mtebc(pb2ap, 0x9b015480);       /* 4MB FLASH */
-               mtebc(pb2cr, 0xff858000);       /* BAS=0xff8 4MB R/W 8-bit */
+               mtebc(PB0AP, 0x9b015480);       /* FLASH/SRAM */
+               mtebc(PB0CR, 0xfff18000);       /* BAS=0xfff 1MB R/W 8-bit */
+               mtebc(PB2AP, 0x9b015480);       /* 4MB FLASH */
+               mtebc(PB2CR, 0xff858000);       /* BAS=0xff8 4MB R/W 8-bit */
        } else {
-               mtebc(pb0ap, 0x9b015480);       /* 4MB FLASH */
-               mtebc(pb0cr, 0xffc58000);       /* BAS=0xffc 4MB R/W 8-bit */
+               mtebc(PB0AP, 0x9b015480);       /* 4MB FLASH */
+               mtebc(PB0CR, 0xffc58000);       /* BAS=0xffc 4MB R/W 8-bit */
 
                /* set CS2 if FLASH_ONBD_N == 0 */
                if (!(status & FLASH_ONBD_N)) {
-                       mtebc(pb2ap, 0x9b015480);       /* FLASH/SRAM */
-                       mtebc(pb2cr, 0xff818000);       /* BAS=0xff8 4MB R/W 8-bit */
+                       mtebc(PB2AP, 0x9b015480);       /* FLASH/SRAM */
+                       mtebc(PB2CR, 0xff818000);       /* BAS=0xff8 4MB R/W 8-bit */
                }
        }
 
@@ -104,7 +104,7 @@ int checkboard(void)
        return (0);
 }
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        long dram_size = 0;
 
@@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose)
         * The ebony board is always configured as the host & requires the
         * PCI arbiter to be enabled.
         *--------------------------------------------------------------------------*/
-       strap = mfdcr(cpc0_strp1);
+       strap = mfdcr(CPC0_STRP1);
        if ((strap & 0x00100000) == 0) {
                printf("PCI: CPC0_STRP1[PAE] not set.\n");
                return 0;
@@ -204,7 +204,7 @@ int pci_pre_init(struct pci_controller *hose)
  *     may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
        /*--------------------------------------------------------------------------+
@@ -219,7 +219,7 @@ void pci_target_init(struct pci_controller *hose)
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
      * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
        out32r(PCIX0_PIM0LAH, 0);
        out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
@@ -228,12 +228,12 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
        out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host