/*
* GPIO0 setup (select GPIO or alternate function)
*/
- out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
- out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
- out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+ out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
*/
- out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
- out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
- out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
- out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
- out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
- out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
- out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
+ out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
+ out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
+ out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
+ out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
+ out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
+ out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
+ out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
}
int board_early_init_f(void)
{
unsigned int reg;
+#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR_PINSTP, reg);
+ mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
+#endif
acadia_gpio_init();
+ /* Configure 405EZ for NAND usage */
+ mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+ mfsdr(SDR0_ULTRA0, reg);
+ reg &= ~SDR_ULTRA0_CSN_MASK;
+ reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
+ SDR_ULTRA0_NDGPIOBP |
+ SDR_ULTRA0_EBCRDYEN |
+ SDR_ULTRA0_NFSRSTEN;
+ mtsdr(SDR0_ULTRA0, reg);
+
/* USB Host core needs this bit set */
- mfsdr(sdrultra1, reg);
- mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+ mfsdr(SDR0_ULTRA1, reg);
+ mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
int misc_init_f(void)
{
/* Set EPLD to take PHY out of reset */
- out8(CFG_CPLD_BASE + 0x05, 0x00);
+ out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
udelay(100000);
return 0;
int checkboard(void)
{
char *s = getenv("serial#");
+ u8 rev;
+
+ rev = in8(CONFIG_SYS_CPLD_BASE + 0);
+ printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
- printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);