Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash

[platform/kernel/u-boot.git] / board / RRvision / RRvision.c

diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c
index f46bb9e..d94e238 100644 (file)
--- a/board/RRvision/RRvision.c
+++ b/board/RRvision/RRvision.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2001-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -93,14 +77,16 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
-       char *s = getenv ("serial#");
+       char buf[64];
+       int i;
+       int l = getenv_f("serial#", buf, sizeof(buf));
 
        puts ("Board: RRvision ");
 
-       for (; s && *s; ++s) {
-               if (*s == ' ')
+       for (i=0; i < l; ++i) {
+               if (buf[i] == ' ')
                        break;
-               putc (*s);
+               putc (buf[i]);
        }
 
        putc ('\n');
@@ -110,9 +96,9 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        unsigned long reg;
        long int size8, size9;
@@ -126,17 +112,17 @@ long int initdram (int board_type)
         * with two SDRAM banks or four cycles every 31.2 us with one
         * bank. It will be adjusted after memory sizing.
         */
-       memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+       memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
        memctl->memc_mar = 0x00000088;
 
        /*
         * Map controller bank 1 the SDRAM bank 2 at physical address 0.
         */
-       memctl->memc_or1 = CFG_OR2_PRELIM;
-       memctl->memc_br1 = CFG_BR2_PRELIM;
+       memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
+       memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
 
-       memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
+       memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 
        udelay (200);
 
@@ -156,7 +142,7 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL,
+       size8 = dram_size (CONFIG_SYS_MAMR_8COL,
                           SDRAM_BASE2_PRELIM,
                           SDRAM_MAX_SIZE);
 
@@ -165,7 +151,7 @@ long int initdram (int board_type)
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL,
+       size9 = dram_size (CONFIG_SYS_MAMR_9COL,
                           SDRAM_BASE2_PRELIM,
                           SDRAM_MAX_SIZE);
 
@@ -174,7 +160,7 @@ long int initdram (int board_type)
 /*             debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
        } else {                        /* back to 8 columns            */
                size = size8;
-               memctl->memc_mamr = CFG_MAMR_8COL;
+               memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
                udelay (500);
 /*             debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
        }
@@ -187,15 +173,15 @@ long int initdram (int board_type)
         */
        if (size < 0x02000000) {
                /* reduce to 15.6 us (62.4 us / quad) */
-               memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+               memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
                udelay (1000);
        }
 
        /*
         * Final mapping
         */
-       memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-       memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+       memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+       memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
        /*
         * No bank 1
@@ -206,7 +192,7 @@ long int initdram (int board_type)
 
        /* adjust refresh rate depending on SDRAM type, one bank */
        reg = memctl->memc_mptpr;
-       reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
+       reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
        memctl->memc_mptpr = reg;
 
        udelay (10000);
@@ -227,7 +213,7 @@ long int initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
                                                   long int maxsize)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
 
        memctl->memc_mamr = mamr_value;