-/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009
- Free Software Foundation, Inc.
+/* Copyright (C) 1998-2014 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
}
static const char*
+ins_cnt6a (const struct ia64_operand *self, ia64_insn value,
+ ia64_insn *code)
+{
+ if (value < 1 || value > 64)
+ return "value must be between 1 and 64";
+ return ins_immu (self, value - 1, code);
+}
+
+static const char*
+ext_cnt6a (const struct ia64_operand *self, ia64_insn code,
+ ia64_insn *valuep)
+{
+ const char *result;
+
+ result = ext_immu (self, code, valuep);
+ if (result)
+ return result;
+
+ *valuep = *valuep + 1;
+ return 0;
+}
+
+static const char*
+ins_strd5b (const struct ia64_operand *self, ia64_insn value,
+ ia64_insn *code)
+{
+ if ( value & 0x3f )
+ return "value must be a multiple of 64";
+ return ins_imms_scaled (self, value, code, 6);
+}
+
+static const char*
+ext_strd5b (const struct ia64_operand *self, ia64_insn code,
+ ia64_insn *valuep)
+{
+ return ext_imms_scaled (self, code, valuep, 6);
+}
+
+
+static const char*
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
BFD_HOST_64_BIT val = value;
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
"a general register r0-r3" },
+ { REG, ins_reg, ext_reg, "dahr", {{ 3, 23}}, 0, /* DAHR */
+ "a dahr register dahr0-7" },
/* memory operands: */
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
"a pmc register" },
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
"a pmd register" },
+ { IND, ins_reg, ext_reg, "dahr", {{7, 20}}, 0, /* DAHR_R3 */
+ "a dahr register" },
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
"an rr register" },
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
"a 14-bit integer (-8192-8191)" },
+ { ABS, ins_immu, ext_immu, 0, /* IMMU16 */
+ {{4, 6}, {11, 12}, { 1, 36}}, UDEC,
+ "a 16-bit unsigned" },
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
"a 17-bit integer (-65536-65535)" },
+ { ABS, ins_immu, ext_immu, 0, /* IMMU19 */
+ {{4, 6}, {14, 12}, { 1, 36}}, UDEC,
+ "a 19-bit unsigned" },
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
"a 21-bit unsigned" },
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
{ ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
"ldxmov target" },
+ { ABS, ins_cnt6a, ext_cnt6a, 0, {{6, 6}}, UDEC, /* CNT6a */
+ "lfetch count" },
+ { ABS, ins_strd5b, ext_strd5b, 0, {{5, 13}}, SDEC, /* STRD5b*/
+ "lfetch stride" },
};