x86/platform/intel-mid: Remove per platform code

[platform/kernel/linux-rpi.git] / arch / x86 / platform / intel-mid / intel-mid.c

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index aac15a4..56f66ea 100644 (file)
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -36,8 +36,6 @@
 #include <asm/apb_timer.h>
 #include <asm/reboot.h>
 
-#include "intel_mid_weak_decls.h"
-
 /*
  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
  * cmdline option x86_intel_mid_timer can be used to override the configuration
@@ -61,10 +59,6 @@
 
 enum intel_mid_timer_options intel_mid_timer_options;
 
-/* intel_mid_ops to store sub arch ops */
-static struct intel_mid_ops *intel_mid_ops;
-/* getter function for sub arch ops*/
-static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
 enum intel_mid_cpu_type __intel_mid_cpu_chip;
 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 
@@ -128,6 +122,7 @@ static void intel_mid_arch_setup(void)
        case 0x3C:
        case 0x4A:
                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
+               x86_platform.legacy.rtc = 1;
                break;
        case 0x27:
        default:
@@ -135,17 +130,7 @@ static void intel_mid_arch_setup(void)
                break;
        }
 
-       if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
-               intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
-       else {
-               intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
-               pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
-       }
-
 out:
-       if (intel_mid_ops->arch_setup)
-               intel_mid_ops->arch_setup();
-
        /*
         * Intel MID platforms are using explicitly defined regulators.
         *