+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Google, Inc
*
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2011 Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ACH_ASM_SANDYBRIDGE_H
#define IED_SIZE 0x400000
/* Northbridge BARs */
-#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
+#define IOMMU_BASE1 0xfed90000ULL
+#define IOMMU_BASE2 0xfed91000ULL
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
#define MCHBAR 0x48
/*
* MCHBAR
*/
-#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
-
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
*/
int bridge_silicon_revision(struct udevice *dev);
-void report_platform_info(struct udevice *dev);
-
-void sandybridge_early_init(int chipset_type);
-
#endif