Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / x86 / include / asm / arch-ivybridge / sandybridge.h

diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c960525..a3a507f 100644 (file)
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2014 Google, Inc
  *
@@ -5,8 +6,6 @@
  *
  * Copyright (C) 2007-2008 coresystems GmbH
  * Copyright (C) 2011 Google Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef _ACH_ASM_SANDYBRIDGE_H
@@ -38,13 +37,15 @@
 #define IED_SIZE       0x400000
 
 /* Northbridge BARs */
-#define DEFAULT_MCHBAR         0xfed10000      /* 16 KB */
 #define DEFAULT_DMIBAR         0xfed18000      /* 4 KB */
 #define DEFAULT_EPBAR          0xfed19000      /* 4 KB */
 #define DEFAULT_RCBABASE       0xfed1c000
 /* 4 KB per PCIe device */
 #define DEFAULT_PCIEXBAR       CONFIG_PCIE_ECAM_BASE
 
+#define IOMMU_BASE1            0xfed90000ULL
+#define IOMMU_BASE2            0xfed91000ULL
+
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define EPBAR          0x40
 #define MCHBAR         0x48
@@ -97,8 +98,6 @@
 /*
  * MCHBAR
  */
-#define MCHBAR_REG(reg)                (DEFAULT_MCHBAR + (reg))
-
 #define SSKPD          0x5d14  /* 16bit (scratchpad) */
 #define BIOS_RESET_CPL 0x5da8  /* 8bit */
 
@@ -108,13 +107,12 @@
 
 #define DMIBAR_REG(x)  (DEFAULT_DMIBAR + x)
 
-int bridge_silicon_revision(void);
-
-void northbridge_enable(pci_dev_t dev);
-void northbridge_init(pci_dev_t dev);
-
-void report_platform_info(void);
-
-void sandybridge_early_init(int chipset_type);
+/**
+ * bridge_silicon_revision() - Get the Northbridge revision
+ *
+ * @dev:       Northbridge device
+ * @return revision ID (bits 3:0) and bridge ID (bits 7:4)
+ */
+int bridge_silicon_revision(struct udevice *dev);
 
 #endif