perf/x86: Add Meteor Lake support

[platform/kernel/linux-starfive.git] / arch / x86 / events / intel / ds.c

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 88e58b6..e991c54 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -53,6 +53,13 @@ union intel_x86_pebs_dse {
                unsigned int st_lat_locked:1;
                unsigned int ld_reserved3:26;
        };
+       struct {
+               unsigned int mtl_dse:5;
+               unsigned int mtl_locked:1;
+               unsigned int mtl_stlb_miss:1;
+               unsigned int mtl_fwd_blk:1;
+               unsigned int ld_reserved4:24;
+       };
 };
 
 
@@ -135,6 +142,29 @@ void __init intel_pmu_pebs_data_source_adl(void)
        __intel_pmu_pebs_data_source_grt(data_source);
 }
 
+static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source)
+{
+       data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
+       data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
+       data_source[0x0a] = OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, NONE);
+       data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
+       data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD);
+       data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM);
+}
+
+void __init intel_pmu_pebs_data_source_mtl(void)
+{
+       u64 *data_source;
+
+       data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
+       memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
+       __intel_pmu_pebs_data_source_skl(false, data_source);
+
+       data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
+       memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
+       intel_pmu_pebs_data_source_cmt(data_source);
+}
+
 static u64 precise_store_data(u64 status)
 {
        union intel_x86_pebs_dse dse;
@@ -219,24 +249,19 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
 }
 
 /* Retrieve the latency data for e-core of ADL */
-u64 adl_latency_data_small(struct perf_event *event, u64 status)
+static u64 __adl_latency_data_small(struct perf_event *event, u64 status,
+                                    u8 dse, bool tlb, bool lock, bool blk)
 {
-       union intel_x86_pebs_dse dse;
        u64 val;
 
        WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big);
 
-       dse.val = status;
-
-       val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
+       dse &= PERF_PEBS_DATA_SOURCE_MASK;
+       val = hybrid_var(event->pmu, pebs_data_source)[dse];
 
-       /*
-        * For the atom core on ADL,
-        * bit 4: lock, bit 5: TLB access.
-        */
-       pebs_set_tlb_lock(&val, dse.ld_locked, dse.ld_stlb_miss);
+       pebs_set_tlb_lock(&val, tlb, lock);
 
-       if (dse.ld_data_blk)
+       if (blk)
                val |= P(BLK, DATA);
        else
                val |= P(BLK, NA);
@@ -244,6 +269,29 @@ u64 adl_latency_data_small(struct perf_event *event, u64 status)
        return val;
 }
 
+u64 adl_latency_data_small(struct perf_event *event, u64 status)
+{
+       union intel_x86_pebs_dse dse;
+
+       dse.val = status;
+
+       return __adl_latency_data_small(event, status, dse.ld_dse,
+                                       dse.ld_locked, dse.ld_stlb_miss,
+                                       dse.ld_data_blk);
+}
+
+/* Retrieve the latency data for e-core of MTL */
+u64 mtl_latency_data_small(struct perf_event *event, u64 status)
+{
+       union intel_x86_pebs_dse dse;
+
+       dse.val = status;
+
+       return __adl_latency_data_small(event, status, dse.mtl_dse,
+                                       dse.mtl_stlb_miss, dse.mtl_locked,
+                                       dse.mtl_fwd_blk);
+}
+
 static u64 load_latency_data(struct perf_event *event, u64 status)
 {
        union intel_x86_pebs_dse dse;