Merge tag 'perf-core-2023-08-28' of git://git.kernel.org/pub/scm/linux/kernel/git...

[platform/kernel/linux-starfive.git] / arch / x86 / events / intel / core.c

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2a284ba..fa355d3 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2129,6 +2129,17 @@ static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
        EVENT_EXTRA_END
 };
 
+EVENT_ATTR_STR(topdown-retiring,       td_retiring_cmt,        "event=0x72,umask=0x0");
+EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_cmt,        "event=0x73,umask=0x0");
+
+static struct attribute *cmt_events_attrs[] = {
+       EVENT_PTR(td_fe_bound_tnt),
+       EVENT_PTR(td_retiring_cmt),
+       EVENT_PTR(td_bad_spec_cmt),
+       EVENT_PTR(td_be_bound_tnt),
+       NULL
+};
+
 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
        /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
        INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
@@ -4847,6 +4858,8 @@ PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 
 PMU_FORMAT_ATTR(frontend, "config1:0-23");
 
+PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
+
 static struct attribute *intel_arch3_formats_attr[] = {
        &format_attr_event.attr,
        &format_attr_umask.attr,
@@ -4877,6 +4890,13 @@ static struct attribute *slm_format_attr[] = {
        NULL
 };
 
+static struct attribute *cmt_format_attr[] = {
+       &format_attr_offcore_rsp.attr,
+       &format_attr_ldlat.attr,
+       &format_attr_snoop_rsp.attr,
+       NULL
+};
+
 static struct attribute *skl_format_attr[] = {
        &format_attr_frontend.attr,
        NULL,
@@ -5656,7 +5676,6 @@ static struct attribute *adl_hybrid_extra_attr[] = {
        NULL
 };
 
-PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63");
 FORMAT_ATTR_HYBRID(snoop_rsp,  hybrid_small);
 
 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
@@ -6174,7 +6193,7 @@ __init int intel_pmu_init(void)
                name = "Tremont";
                break;
 
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
                x86_pmu.mid_ack = true;
                memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
@@ -6204,6 +6223,37 @@ __init int intel_pmu_init(void)
                name = "gracemont";
                break;
 
+       case INTEL_FAM6_ATOM_CRESTMONT:
+       case INTEL_FAM6_ATOM_CRESTMONT_X:
+               x86_pmu.mid_ack = true;
+               memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
+                      sizeof(hw_cache_event_ids));
+               memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
+                      sizeof(hw_cache_extra_regs));
+               hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
+
+               x86_pmu.event_constraints = intel_slm_event_constraints;
+               x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
+               x86_pmu.extra_regs = intel_cmt_extra_regs;
+
+               x86_pmu.pebs_aliases = NULL;
+               x86_pmu.pebs_prec_dist = true;
+               x86_pmu.lbr_pt_coexist = true;
+               x86_pmu.pebs_block = true;
+               x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+               x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
+
+               intel_pmu_pebs_data_source_cmt();
+               x86_pmu.pebs_latency_data = mtl_latency_data_small;
+               x86_pmu.get_event_constraints = cmt_get_event_constraints;
+               x86_pmu.limit_period = spr_limit_period;
+               td_attr = cmt_events_attrs;
+               mem_attr = grt_mem_attrs;
+               extra_attr = cmt_format_attr;
+               pr_cont("Crestmont events, ");
+               name = "crestmont";
+               break;
+
        case INTEL_FAM6_WESTMERE:
        case INTEL_FAM6_WESTMERE_EP:
        case INTEL_FAM6_WESTMERE_EX: