Merge branch 'master' of git://git.denx.de/u-boot

[platform/kernel/u-boot.git] / arch / x86 / cpu / quark / quark.c

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 3ddf079..f737e19 100644 (file)
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -8,6 +8,8 @@
 #include <mmc.h>
 #include <asm/io.h>
 #include <asm/irq.h>
+#include <asm/mrccache.h>
+#include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
@@ -34,6 +36,55 @@ static void unprotect_spi_flash(void)
        qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
 }
 
+static void quark_setup_mtrr(void)
+{
+       u32 base, mask;
+       int i;
+
+       disable_caches();
+
+       /* mark the VGA RAM area as uncacheable */
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+       /* mark other fixed range areas as cacheable */
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
+                      MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+       for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
+               msg_port_write(MSG_PORT_HOST_BRIDGE, i,
+                              MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+       /* variable range MTRR#0: ROM area */
+       mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
+       base = CONFIG_SYS_TEXT_BASE & mask;
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
+                      base | MTRR_TYPE_WRBACK);
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
+                      mask | MTRR_PHYS_MASK_VALID);
+
+       /* variable range MTRR#1: eSRAM area */
+       mask = ~(ESRAM_SIZE - 1);
+       base = CONFIG_ESRAM_BASE & mask;
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
+                      base | MTRR_TYPE_WRBACK);
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
+                      mask | MTRR_PHYS_MASK_VALID);
+
+       /* enable both variable and fixed range MTRRs */
+       msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
+                      MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
+
+       enable_caches();
+}
+
 static void quark_setup_bars(void)
 {
        /* GPIO - D31:F0:R44h */
@@ -134,6 +185,43 @@ static void quark_usb_early_init(void)
        msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
 }
 
+static void quark_thermal_early_init(void)
+{
+       /* The sequence below comes from Quark firmware writer guide */
+
+       /* thermal sensor mode config */
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+                               (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+                               (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
+                               (1 << 12), 1 << 9);
+       msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
+       msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
+       msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
+                               (1 << 8) | (1 << 9), 1 << 8);
+       msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
+       msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
+                               0x7ff800, 0xc8 << 11);
+
+       /* thermal monitor catastrophic trip set point (105 celsius) */
+       msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
+
+       /* thermal monitor catastrophic trip clear point (0 celsius) */
+       msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
+
+       /* take thermal sensor out of reset */
+       msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
+
+       /* enable thermal monitor */
+       msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
+
+       /* lock all thermal configuration */
+       msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
+}
+
 static void quark_enable_legacy_seg(void)
 {
        msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
@@ -154,6 +242,13 @@ int arch_cpu_init(void)
                return ret;
 
        /*
+        * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
+        * are accessed indirectly via the message port and not the traditional
+        * MSR mechanism. Only UC, WT and WB cache types are supported.
+        */
+       quark_setup_mtrr();
+
+       /*
         * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
         * which need be initialized with suggested values
         */
@@ -173,6 +268,9 @@ int arch_cpu_init(void)
        /* Initialize USB2 PHY */
        quark_usb_early_init();
 
+       /* Initialize thermal sensor */
+       quark_thermal_early_init();
+
        /* Turn on legacy segments (A/B/E/F) decode to system RAM */
        quark_enable_legacy_seg();
 
@@ -271,6 +369,15 @@ void cpu_irq_init(void)
 
 int arch_misc_init(void)
 {
+#ifdef CONFIG_ENABLE_MRC_CACHE
+       /*
+        * We intend not to check any return value here, as even MRC cache
+        * is not saved successfully, it is not a severe error that will
+        * prevent system from continuing to boot.
+        */
+       mrccache_save();
+#endif
+
        return pirq_init();
 }
 
@@ -293,3 +400,12 @@ void board_final_cleanup(void)
 
        return;
 }
+
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+       return mrccache_reserve();
+#else
+       return 0;
+#endif
+}