Merge branch 'master' of git://git.denx.de/u-boot

[platform/kernel/u-boot.git] / arch / x86 / cpu / ivybridge / cpu.c

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index e6ef481..0e6512c 100644 (file)
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <asm/cpu.h>
@@ -91,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
 
        /* Issue warm reset, will be "CPU only" due to soft reset data */
        outb(0x0, PORT_RESET);
-       outb(0x6, PORT_RESET);
+       outb(SYS_RST | RST_CPU, PORT_RESET);
        cpu_hlt();
 
        /* Not reached */
@@ -126,21 +127,22 @@ int arch_cpu_init_dm(void)
 {
        const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
+       struct udevice *bus;
        int node;
        int ret;
 
-       post_code(POST_CPU_INIT);
-       timer_set_base(rdtsc());
-
-       ret = x86_cpu_init_f();
+       post_code(0x70);
+       ret = uclass_get_device(UCLASS_PCI, 0, &bus);
+       post_code(0x71);
        if (ret)
                return ret;
+       post_code(0x72);
+       hose = dev_get_uclass_priv(bus);
 
-       ret = pci_early_init_hose(&hose);
-       if (ret)
-               return ret;
+       /* TODO(sjg@chromium.org): Get rid of gd->hose */
+       gd->hose = hose;
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
        if (node < 0)
                return -ENOENT;
        ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
@@ -284,8 +286,7 @@ int print_cpuinfo(void)
 
                /* System is not happy after keyboard reset... */
                debug("Issuing CF9 warm reset\n");
-               outb(0x6, 0xcf9);
-               cpu_hlt();
+               reset_cpu(0);
        }
 
        /* Early chipset init required before RAM init can work */
@@ -339,3 +340,10 @@ int print_cpuinfo(void)
 
        return 0;
 }
+
+void board_debug_uart_init(void)
+{
+       /* This enables the debug UART */
+       pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
+                            PCI_SIZE_16);
+}