Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / x86 / cpu / ivybridge / bd82x6x.c

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 2591b20..ed9bce6 100644 (file)
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <dm.h>
@@ -9,16 +8,26 @@
 #include <fdtdec.h>
 #include <malloc.h>
 #include <pch.h>
+#include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
-#include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
-#define BIOS_CTRL      0xdc
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_BASE              0x48
+#define BIOS_CTRL              0xdc
 
+#define RCBA_AUDIO_CONFIG      0x2030
+#define RCBA_AUDIO_CONFIG_HDA  BIT(31)
+#define RCBA_AUDIO_CONFIG_MASK 0xfe
+
+#ifndef CONFIG_HAVE_FSP
 static int pch_revision_id = -1;
 static int pch_type = -1;
 
@@ -149,32 +158,17 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
 
 static int bd82x6x_probe(struct udevice *dev)
 {
-       const void *blob = gd->fdt_blob;
-       int gma_node;
-       int ret;
-
        if (!(gd->flags & GD_FLG_RELOC))
                return 0;
 
        /* Cause the SATA device to do its init */
-       uclass_first_device(UCLASS_DISK, &dev);
-
-       gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
-       if (gma_node < 0) {
-               debug("%s: Cannot find GMA node\n", __func__);
-               return -EINVAL;
-       }
-       ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
-       if (ret)
-               return ret;
-       ret = gma_func0_init(dev, blob, gma_node);
-       if (ret)
-               return ret;
+       uclass_first_device(UCLASS_AHCI, &dev);
 
        return 0;
 }
+#endif /* CONFIG_HAVE_FSP */
 
-static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
        u32 rcba;
 
@@ -186,33 +180,65 @@ static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
        return 0;
 }
 
-static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
-       return PCHV_9;
+       return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
 }
 
-static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
 {
-       uint8_t bios_cntl;
-
-       /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
-       dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
-       if (protect) {
-               bios_cntl &= ~BIOS_CTRL_BIOSWE;
-               bios_cntl |= BIT(5);
-       } else {
-               bios_cntl |= BIOS_CTRL_BIOSWE;
-               bios_cntl &= ~BIT(5);
+       u32 base;
+
+       /*
+        * GPIO_BASE moved to its current offset with ICH6, but prior to
+        * that it was unused (or undocumented). Check that it looks
+        * okay: not all ones or zeros.
+        *
+        * Note we don't need check bit0 here, because the Tunnel Creek
+        * GPIO base address register bit0 is reserved (read returns 0),
+        * while on the Ivybridge the bit0 is used to indicate it is an
+        * I/O space.
+        */
+       dm_pci_read_config32(dev, GPIO_BASE, &base);
+       if (base == 0x00000000 || base == 0xffffffff) {
+               debug("%s: unexpected BASE value\n", __func__);
+               return -ENODEV;
        }
-       dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+       /*
+        * Okay, I guess we're looking at the right device. The actual
+        * GPIO registers are in the PCI device's I/O space, starting
+        * at the offset that we just read. Bit 0 indicates that it's
+        * an I/O address, not a memory address, so mask that off.
+        */
+       *gbasep = base & 1 ? base & ~3 : base & ~15;
 
        return 0;
 }
 
+static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
+                        int size)
+{
+       u32 rcba, val;
+
+       switch (req) {
+       case PCH_REQ_HDA_CONFIG:
+               dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+               val = readl(rcba + RCBA_AUDIO_CONFIG);
+               if (!(val & RCBA_AUDIO_CONFIG_HDA))
+                       return -ENOENT;
+
+               return val & RCBA_AUDIO_CONFIG_MASK;
+       default:
+               return -ENOSYS;
+       }
+}
+
 static const struct pch_ops bd82x6x_pch_ops = {
-       .get_sbase      = bd82x6x_pch_get_sbase,
-       .get_version    = bd82x6x_pch_get_version,
+       .get_spi_base   = bd82x6x_pch_get_spi_base,
        .set_spi_protect = bd82x6x_set_spi_protect,
+       .get_gpio_base  = bd82x6x_get_gpio_base,
+       .ioctl          = bd82x6x_ioctl,
 };
 
 static const struct udevice_id bd82x6x_ids[] = {
@@ -224,6 +250,8 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
        .name           = "bd82x6x",
        .id             = UCLASS_PCH,
        .of_match       = bd82x6x_ids,
+#ifndef CONFIG_HAVE_FSP
        .probe          = bd82x6x_probe,
+#endif
        .ops            = &bd82x6x_pch_ops,
 };