/* DS: data, read/write, 4 GB, base 0 */
gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
- /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
+ /*
+ * FS: data, read/write, sizeof (Global Data Pointer),
+ * base (Global Data Pointer)
+ */
new_gd->arch.gd_addr = new_gd;
- gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
- (ulong)&new_gd->arch.gd_addr, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
+ (ulong)&new_gd->arch.gd_addr,
+ sizeof(new_gd->arch.gd_addr) - 1);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
return 0;
}
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+ u32 *ptr, *end;
+
+ size /= 4;
+ for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+ if (*ptr == 0x4f49424c) /* "LBIO" */
+ return (long)ptr;
+ }
+
+ return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+ long addr;
+
+ /* We look for LBIO in the first 4K of RAM and again at 960KB */
+ addr = detect_coreboot_table_at(0x0, 0x1000);
+ if (addr < 0)
+ addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+ return addr;
+}
+
int x86_cpu_reinit_f(void)
{
setup_identity();
setup_pci_ram_top();
+ if (locate_coreboot_table() >= 0)
+ gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
}