Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / x86 / cpu / i386 / cpu.c

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 90b546e..0312a26 100644 (file)
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -19,7 +19,10 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <init.h>
 #include <malloc.h>
+#include <spl.h>
 #include <asm/control_regs.h>
 #include <asm/cpu.h>
 #include <asm/mp.h>
@@ -57,6 +60,8 @@ struct cpuinfo_x86 {
        uint8_t x86_mask;
 };
 
+/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
+#ifndef CONFIG_TPL_BUILD
 /*
  * List of cpu vendor strings along with their normalized
  * id values.
@@ -77,6 +82,7 @@ static const struct {
        { X86_VENDOR_NSC,       "Geode by NSC", },
        { X86_VENDOR_SIS,       "SiS SiS SiS ", },
 };
+#endif
 
 static void load_ds(u32 segment)
 {
@@ -130,10 +136,14 @@ void arch_setup_gd(gd_t *new_gd)
        /* DS: data, read/write, 4 GB, base 0 */
        gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
 
-       /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
+       /*
+        * FS: data, read/write, sizeof (Global Data Pointer),
+        * base (Global Data Pointer)
+        */
        new_gd->arch.gd_addr = new_gd;
-       gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
-                    (ulong)&new_gd->arch.gd_addr, 0xfffff);
+       gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
+                                       (ulong)&new_gd->arch.gd_addr,
+                                       sizeof(new_gd->arch.gd_addr) - 1);
 
        /* 16-bit CS: code, read/execute, 64 kB, base 0 */
        gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
@@ -198,6 +208,7 @@ static inline int test_cyrix_52div(void)
        return (unsigned char) (test >> 8) == 0x02;
 }
 
+#ifndef CONFIG_TPL_BUILD
 /*
  *     Detect a NexGen CPU running without BIOS hypercode new enough
  *     to have CPUID. (Thanks to Herbert Oppmann)
@@ -218,6 +229,7 @@ static int deep_magic_nexgen_probe(void)
                : "=a" (ret) : : "cx", "dx");
        return  ret;
 }
+#endif
 
 static bool has_cpuid(void)
 {
@@ -229,6 +241,7 @@ static bool has_mtrr(void)
        return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
 }
 
+#ifndef CONFIG_TPL_BUILD
 static int build_vendor_name(char *vendor_name)
 {
        struct cpuid_result result;
@@ -241,14 +254,40 @@ static int build_vendor_name(char *vendor_name)
 
        return result.eax;
 }
+#endif
 
 static void identify_cpu(struct cpu_device_id *cpu)
 {
+       cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+       /*
+        * Do a quick and dirty check to save space - Intel and AMD only and
+        * just the vendor. This is enough for most TPL code.
+        */
+       if (spl_phase() == PHASE_TPL) {
+               struct cpuid_result result;
+
+               result = cpuid(0x00000000);
+               switch (result.ecx >> 24) {
+               case 'l': /* GenuineIntel */
+                       cpu->vendor = X86_VENDOR_INTEL;
+                       break;
+               case 'D': /* AuthenticAMD */
+                       cpu->vendor = X86_VENDOR_AMD;
+                       break;
+               default:
+                       cpu->vendor = X86_VENDOR_ANY;
+                       break;
+               }
+               return;
+       }
+
+/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
+#ifndef CONFIG_TPL_BUILD
        char vendor_name[16];
        int i;
 
        vendor_name[0] = '\0'; /* Unset */
-       cpu->device = 0; /* fix gcc 4.4.4 warning */
 
        /* Find the id and vendor_name */
        if (!has_cpuid()) {
@@ -264,9 +303,8 @@ static void identify_cpu(struct cpu_device_id *cpu)
                /* Detect NexGen with old hypercode */
                else if (deep_magic_nexgen_probe())
                        memcpy(vendor_name, "NexGenDriven", 13);
-       }
-       if (has_cpuid()) {
-               int  cpuid_level;
+       } else {
+               int cpuid_level;
 
                cpuid_level = build_vendor_name(vendor_name);
                vendor_name[12] = '\0';
@@ -286,6 +324,7 @@ static void identify_cpu(struct cpu_device_id *cpu)
                        break;
                }
        }
+#endif
 }
 
 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
@@ -385,6 +424,14 @@ static void setup_mtrr(void)
        }
 }
 
+int x86_cpu_init_tpl(void)
+{
+       setup_cpu_features();
+       setup_identity();
+
+       return 0;
+}
+
 int x86_cpu_init_f(void)
 {
        if (ll_boot_init())
@@ -400,10 +447,37 @@ int x86_cpu_init_f(void)
        return 0;
 }
 
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+       u32 *ptr, *end;
+
+       size /= 4;
+       for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+               if (*ptr == 0x4f49424c) /* "LBIO" */
+                       return (long)ptr;
+       }
+
+       return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+       long addr;
+
+       /* We look for LBIO in the first 4K of RAM and again at 960KB */
+       addr = detect_coreboot_table_at(0x0, 0x1000);
+       if (addr < 0)
+               addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+       return addr;
+}
+
 int x86_cpu_reinit_f(void)
 {
        setup_identity();
        setup_pci_ram_top();
+       if (locate_coreboot_table() >= 0)
+               gd->flags |= GD_FLG_SKIP_LL_INIT;
 
        return 0;
 }