Coding Style cleanup: remove trailing white space

[platform/kernel/u-boot.git] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index f262800..e24f13a 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -3,39 +3,23 @@
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/io.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
 #include <asm/arch/timestamp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
 /*
  * Miscellaneous platform dependent initializations
  */
@@ -68,11 +52,32 @@ int board_early_init_r(void)
 
 void show_boot_progress(int val)
 {
+#if MIN_PORT80_KCLOCKS_DELAY
+       /*
+        * Scale the time counter reading to avoid using 64 bit arithmetics.
+        * Can't use get_timer() here becuase it could be not yet
+        * initialized or even implemented.
+        */
+       if (!gd->arch.tsc_prev) {
+               gd->arch.tsc_base_kclocks = rdtsc() / 1000;
+               gd->arch.tsc_prev = 0;
+       } else {
+               uint32_t now;
+
+               do {
+                       now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
+               } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
+               gd->arch.tsc_prev = now;
+       }
+#endif
+       outb(val, 0x80);
 }
 
-
 int last_stage_init(void)
 {
+       if (gd->flags & GD_FLG_COLD_BOOT)
+               timestamp_add_to_bootstage();
+
        return 0;
 }
 
@@ -88,10 +93,8 @@ int board_eth_init(bd_t *bis)
        return pci_eth_init(bis);
 }
 
-void setup_pcat_compatibility()
-{
-}
-
+#define MTRR_TYPE_WP          5
+#define MTRRcap_MSR           0xfe
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -99,11 +102,33 @@ int board_final_cleanup(void)
 {
        /* Un-cache the ROM so the kernel has one
         * more MTRR available.
+        *
+        * Coreboot should have assigned this to the
+        * top available variable MTRR.
         */
-       disable_caches();
-       wrmsrl(MTRRphysBase_MSR(7), 0);
-       wrmsrl(MTRRphysMask_MSR(7), 0);
-       enable_caches();
+       u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
+       u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+
+       /* Make sure this MTRR is the correct Write-Protected type */
+       if (top_type == MTRR_TYPE_WP) {
+               disable_caches();
+               wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
+               wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
+               enable_caches();
+       }
+
+       /* Issue SMI to Coreboot to lock down ME and registers */
+       printf("Finalizing Coreboot\n");
+       outb(0xcb, 0xb2);
 
        return 0;
 }
+
+void panic_puts(const char *str)
+{
+       NS16550_t port = (NS16550_t)0x3f8;
+
+       NS16550_init(port, 1);
+       while (*str)
+               NS16550_putc(port, *str++);
+}