riscv: Implement non-coherent DMA support via SiFive cache flushing

[platform/kernel/linux-starfive.git] / arch / riscv / mm / dma-noncoherent.c

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d919efa..e07e53a 100644 (file)
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -9,14 +9,21 @@
 #include <linux/dma-map-ops.h>
 #include <linux/mm.h>
 #include <asm/cacheflush.h>
+#include <soc/sifive/sifive_ccache.h>
 
 static bool noncoherent_supported;
 
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
                              enum dma_data_direction dir)
 {
-       void *vaddr = phys_to_virt(paddr);
+       void *vaddr;
 
+       if (sifive_ccache_handle_noncoherent()) {
+               sifive_ccache_flush_range(paddr, size);
+               return;
+       }
+
+       vaddr = phys_to_virt(paddr);
        switch (dir) {
        case DMA_TO_DEVICE:
                ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
@@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
                           enum dma_data_direction dir)
 {
-       void *vaddr = phys_to_virt(paddr);
+       void *vaddr;
+
+       if (sifive_ccache_handle_noncoherent()) {
+               sifive_ccache_flush_range(paddr, size);
+               return;
+       }
 
+       vaddr = phys_to_virt(paddr);
        switch (dir) {
        case DMA_TO_DEVICE:
                break;
@@ -49,10 +62,30 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
        }
 }
 
+void *arch_dma_set_uncached(void *addr, size_t size)
+{
+       if (sifive_ccache_handle_noncoherent())
+               return sifive_ccache_set_uncached(addr, size);
+
+       return addr;
+}
+
+void arch_dma_clear_uncached(void *addr, size_t size)
+{
+       if (sifive_ccache_handle_noncoherent())
+               sifive_ccache_clear_uncached(addr, size);
+}
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
        void *flush_addr = page_address(page);
 
+       if (sifive_ccache_handle_noncoherent()) {
+               memset(flush_addr, 0, size);
+               sifive_ccache_flush_range(__pa(flush_addr), size);
+               return;
+       }
+
        ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
 }