Merge patch series "Add non-coherent DMA support for AX45MP"

[platform/kernel/linux-rpi.git] / arch / riscv / mm / dma-noncoherent.c

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index f269990..b76e7e1 100644 (file)
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -9,15 +9,28 @@
 #include <linux/dma-map-ops.h>
 #include <linux/mm.h>
 #include <asm/cacheflush.h>
+#include <asm/dma-noncoherent.h>
 
 static bool noncoherent_supported __ro_after_init;
 int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
 EXPORT_SYMBOL_GPL(dma_cache_alignment);
 
+struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init = {
+       .wback = NULL,
+       .inv = NULL,
+       .wback_inv = NULL,
+};
+
 static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
        void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+       if (unlikely(noncoherent_cache_ops.wback)) {
+               noncoherent_cache_ops.wback(paddr, size);
+               return;
+       }
+#endif
        ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -25,6 +38,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
        void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+       if (unlikely(noncoherent_cache_ops.inv)) {
+               noncoherent_cache_ops.inv(paddr, size);
+               return;
+       }
+#endif
+
        ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -32,6 +52,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
        void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+       if (unlikely(noncoherent_cache_ops.wback_inv)) {
+               noncoherent_cache_ops.wback_inv(paddr, size);
+               return;
+       }
+#endif
+
        ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -97,6 +124,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
 {
        void *flush_addr = page_address(page);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+       if (unlikely(noncoherent_cache_ops.wback_inv)) {
+               noncoherent_cache_ops.wback_inv(page_to_phys(page), size);
+               return;
+       }
+#endif
+
        ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
 }
 
@@ -128,3 +162,12 @@ void __init riscv_set_dma_cache_alignment(void)
        if (!noncoherent_supported)
                dma_cache_alignment = 1;
 }
+
+void riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops)
+{
+       if (!ops)
+               return;
+
+       noncoherent_cache_ops = *ops;
+}
+EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);