RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA

[platform/kernel/linux-starfive.git] / arch / riscv / kernel / sys_riscv.c

diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index fe8e833..5ca567c 100644 (file)
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -9,6 +9,7 @@
 #include <asm/cacheflush.h>
 #include <asm/hwprobe.h>
 #include <asm/sbi.h>
+#include <asm/switch_to.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 #include <asm-generic/mman-common.h>
@@ -125,6 +126,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
        case RISCV_HWPROBE_KEY_MIMPID:
                hwprobe_arch_id(pair, cpus);
                break;
+       /*
+        * The kernel already assumes that the base single-letter ISA
+        * extensions are supported on all harts, and only supports the
+        * IMA base, so just cheat a bit here and tell that to
+        * userspace.
+        */
+       case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
+               pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
+               break;
+
+       case RISCV_HWPROBE_KEY_IMA_EXT_0:
+               pair->value = 0;
+               if (has_fpu())
+                       pair->value |= RISCV_HWPROBE_IMA_FD;
+
+               if (riscv_isa_extension_available(NULL, c))
+                       pair->value |= RISCV_HWPROBE_IMA_C;
+
+               break;
 
        /*
         * For forward compatibility, unknown keys don't fail the whole