RISC-V: Avoid using per cpu array for ordered booting

[platform/kernel/linux-starfive.git] / arch / riscv / kernel / head.S

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 25baa19..2fc8617 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -11,6 +11,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/csr.h>
+#include <asm/cpu_ops_sbi.h>
 #include <asm/hwcap.h>
 #include <asm/image.h>
 #include "efi-header.S"
@@ -147,18 +148,17 @@ secondary_start_sbi:
        la a3, .Lsecondary_park
        csrw CSR_TVEC, a3
 
-       slli a3, a0, LGREG
-       la a4, __cpu_up_stack_pointer
-       XIP_FIXUP_OFFSET a4
-       la a5, __cpu_up_task_pointer
-       XIP_FIXUP_OFFSET a5
-       add a4, a3, a4
-       add a5, a3, a5
-       REG_L sp, (a4)
-       REG_L tp, (a5)
-
-       .global secondary_start_common
-secondary_start_common:
+       /* a0 contains the hartid & a1 contains boot data */
+       li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
+       XIP_FIXUP_OFFSET a2
+       add a2, a2, a1
+       REG_L tp, (a2)
+       li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
+       XIP_FIXUP_OFFSET a3
+       add a3, a3, a1
+       REG_L sp, (a3)
+
+.Lsecondary_start_common:
 
 #ifdef CONFIG_MMU
        /* Enable virtual memory and relocate to virtual address */
@@ -344,7 +344,7 @@ clear_bss_done:
        beqz tp, .Lwait_for_cpu_up
        fence
 
-       tail secondary_start_common
+       tail .Lsecondary_start_common
 #endif
 
 END(_start_kernel)