RISC-V: Correctly print supported extensions

[platform/kernel/linux-starfive.git] / arch / riscv / kernel / cpufeature.c

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d20..dd3d57e 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -13,6 +13,8 @@
 #include <asm/smp.h>
 #include <asm/switch_to.h>
 
+#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
+
 unsigned long elf_hwcap __read_mostly;
 
 /* Host ISA bitmap */
@@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void)
 {
        struct device_node *node;
        const char *isa;
-       char print_str[BITS_PER_LONG + 1];
+       char print_str[NUM_ALPHA_EXTS + 1];
        size_t i, j, isa_len;
        static unsigned long isa2hwcap[256] = {0};
 
@@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
        }
 
        memset(print_str, 0, sizeof(print_str));
-       for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+       for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
                if (riscv_isa[0] & BIT_MASK(i))
                        print_str[j++] = (char)('a' + i);
        pr_info("riscv: ISA extensions %s\n", print_str);
 
        memset(print_str, 0, sizeof(print_str));
-       for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+       for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
                if (elf_hwcap & BIT_MASK(i))
                        print_str[j++] = (char)('a' + i);
        pr_info("riscv: ELF capabilities %s\n", print_str);