Merge patch series "ISA string parser cleanups"

[platform/kernel/linux-starfive.git] / arch / riscv / kernel / cpu.c

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index e58e93d..a2fc952 100644 (file)
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -23,6 +23,26 @@
  */
 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
 {
+       int cpu;
+
+       *hart = (unsigned long)of_get_cpu_hwid(node, 0);
+       if (*hart == ~0UL) {
+               pr_warn("Found CPU without hart ID\n");
+               return -ENODEV;
+       }
+
+       cpu = riscv_hartid_to_cpuid(*hart);
+       if (cpu < 0)
+               return cpu;
+
+       if (!cpu_possible(cpu))
+               return -ENODEV;
+
+       return 0;
+}
+
+int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart)
+{
        const char *isa;
 
        if (!of_device_is_compatible(node, "riscv")) {
@@ -30,7 +50,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
                return -ENODEV;
        }
 
-       *hart = (unsigned long) of_get_cpu_hwid(node, 0);
+       *hart = (unsigned long)of_get_cpu_hwid(node, 0);
        if (*hart == ~0UL) {
                pr_warn("Found CPU without hart ID\n");
                return -ENODEV;
@@ -45,10 +65,12 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
                pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
                return -ENODEV;
        }
-       if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') {
-               pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
+
+       if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7))
+               return -ENODEV;
+
+       if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7))
                return -ENODEV;
-       }
 
        return 0;
 }
@@ -186,7 +208,11 @@ arch_initcall(riscv_cpuinfo_init);
 static struct riscv_isa_ext_data isa_ext_arr[] = {
        __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
        __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
+       __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
+       __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
+       __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
        __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+       __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
        __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
        __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
        __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),