reg = <0x0 0x100a0000 0x0 0x1000>;
clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
<&clkgen JH7110_SPDIF_CLK_CORE>,
- <&clkgen JH7110_APB0>,
<&clkgen JH7110_AUDIO_ROOT>,
<&clkgen JH7110_MCLK_INNER>;
- clock-names = "spdif-apb", "spdif-core", "apb0",
+ clock-names = "spdif-apb", "spdif-core",
"audroot", "mclk_inner";
resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
reset-names = "rst_apb";
<&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
<&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
<&clkgen JH7110_I2SRX0_3CH_BCLK>,
- <&clkgen JH7110_I2SRX0_3CH_LRCK>;
+ <&clkgen JH7110_I2SRX0_3CH_LRCK>,
+ <&clkgen JH7110_MCLK>,
+ <&i2srx_bclk_ext>,
+ <&i2srx_lrck_ext>;
clock-names = "apb0", "3ch-apb",
"audioroot", "mclk-inner",
"bclk_mst", "3ch-lrck",
- "rx-bclk", "rx-lrck";
+ "rx-bclk", "rx-lrck",
+ "mclk", "bclk-ext",
+ "lrck-ext";
resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
<&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
dmas = <&dma 24 1>;