compatible = "starfive,si5-timers";
reg = <0x0 0x13050000 0x0 0x10000>;
interrupts = <69>, <70>, <71> ,<72>;
- interrupt-names = "timer0", "timer1", "timer2", "timer3";
+ interrupt-names = "timer0", "timer1",
+ "timer2", "timer3";
+ clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
+ <&clkgen JH7110_TIMER_CLK_TIMER1>,
+ <&clkgen JH7110_TIMER_CLK_TIMER2>,
+ <&clkgen JH7110_TIMER_CLK_TIMER3>,
+ <&clkgen JH7110_TIMER_CLK_APB>;
+ clock-names = "timer0", "timer1",
+ "timer2", "timer3", "apb_clk";
clock-frequency = <2000000>;
- status = "disabled";
+ status = "okay";
};
wdog: wdog@13070000 {
interrupt-names = "wdog";
clock-frequency = <2000000>;
clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
- <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
+ <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
clock-names = "core_clk", "apb_clk";
resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
- <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
+ <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
reset-names = "rst_apb", "rst_core";
timeout-sec = <15>;
status = "okay";
i2c6: i2c@12060000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
+ <&clkgen JH7110_I2C6_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U6_DW_I2C_APB>;
interrupts = <51>;
#address-cells = <1>;
#size-cells = <0>;
i2c0: i2c@10030000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
+ <&clkgen JH7110_I2C0_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U0_DW_I2C_APB>;
interrupts = <35>;
#address-cells = <1>;
#size-cells = <0>;
i2c1: i2c@10040000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10040000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
+ <&clkgen JH7110_I2C1_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U1_DW_I2C_APB>;
interrupts = <36>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- ipmscan0: can@130d0000 {
+ can0: can@130d0000 {
compatible = "ipms,can";
- reg = <0x0 0x130d0000 0x0 0x1000>,
- <0x0 0x13030000 0x0 0x10000>;
- reg-names = "reg_base","sys_syscon";
+ reg = <0x0 0x130d0000 0x0 0x1000>;
interrupts = <112>;
- clocks = <&canclk>,
- <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
+ clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
<&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
<&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
- clock-names = "ipms_can_clk",
- "apb_clk",
+ clock-names = "apb_clk",
"core_clk",
"timer_clk";
resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
reset-names = "rst_apb",
"rst_core",
"rst_timer";
+ starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
+ syscon,can_or_canfd = <0>;
status = "disabled";
};
- ipmscan1: can@130c0000 {
+ can1: can@130e0000 {
compatible = "ipms,can";
- reg = <0x0 0x130c0000 0x0 0x1000>,
- <0x0 0x13030000 0x0 0x10000>;
- reg-names = "reg_base","sys_syscon";
+ reg = <0x0 0x130e0000 0x0 0x1000>;
interrupts = <113>;
- clocks = <&canclk>,
- <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
+ clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
<&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
<&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
- clock-names = "ipms_can_clk",
- "apb_clk",
+ clock-names = "apb_clk",
"core_clk",
"timer_clk";
resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
reset-names = "rst_apb",
"rst_core",
"rst_timer";
+ starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
+ syscon,can_or_canfd = <0>;
status = "disabled";
};